BS616UV2011TI [BSI]
Ultra Low Power/Voltage CMOS SRAM 128K X 16 bit; 超低功率/电压CMOS SRAM 128K ×16位
| 型号： | BS616UV2011TI |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 128K X 16 bit |
| 文件： | 总11页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616UV2011
FEATURES
DESCRIPTION
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
The BS616UV2011 is a high performance, Ultra low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.08uA and maximum access time of 70/100ns in 2.0V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
Vcc = 2.0 V
C-grade: 15mA (Max.) operating current
I-grade: 20mA (Max.) operating current
0.08uA (Typ.) CMOS standby current
C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 3.0 V
• High speed access time :
-70
-10
70ns (Max.) at Vcc = 2.0V
100ns (Max.) at Vcc = 2.0V
The BS616UV2011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV2011 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package , JEDEC standard 48-pin TSOP Type I package
and 48-ball BGA package.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
(
ns )
( I
( I
, Max )
CC
CCSB1, Max )
PKG TYPE
DICE
Vcc=
2.0V
Vcc=
Vcc=
3.0V
Vcc=
2.0V
Vcc=
3.0V
2.0V
BS616UV2011DC
BS616UV2011EC
BS616UV2011TC
BS616UV2011AC
BS616UV2011DI
BS616UV2011EI
BS616UV2011TI
BS616UV2011AI
TSOP2-44
TSOP1-48
BGA-48-0608
DICE
+0O C to +70OC
-40O C to +85OC
1.8V ~ 3.6V
1.8V ~ 3.6V
70/100
0.5uA
0.7uA
15mA
20mA
TSOP2-44
TSOP1-48
BGA-48-0608
70/100
1uA
1.5uA
20mA
25mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
A4
A5
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
A6
3
A2
A7
A8
A13
4
A1
OE
5
A0
UB
6
CE
LB
A15
A16
A14
A12
A7
Address
7
DQ0
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
20
8
1024
DQ1
9
DQ2
Input
Row
Decoder
10
Memory Array
1024 x 2048
DQ3
BS616UV2011EC
BS616UV2011EI
11
12
13
14
15
16
17
18
19
20
21
22
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
Buffer
A6
A5
A4
2048
A16
A15
A14
A13
A12
A8
A9
Data
A10
A11
NC
16
16
16
Column I/O
Input
DQ0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
Data
16
Output
A
B
C
D
E
F
LB
D8
D9
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
Buffer
Column Decoder
DQ15
CE
D1
14
CE
WE
OE
UB
D10
D11
D12
D13
A5
A6
D2
Control
Address Input Buffer
VSS
VCC
N.C.
N.C.
A14
A12
A9
A7
D3
VCC
VSS
LB
A11 A9 A3 A2 A1
A0 A10
A16
A15
A13
A10
D4
Vcc
Gnd
D14
D15
N.C.
D5
D6
D7
G
H
WE
A11
N.C.
A8
N.C.
48-ball BGA top view
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.5
April 2002
R0201-BS616UV2011
1
BSI
BS616UV2011
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
Not selected
X
X
High Z
High Z
ICCSB, ICCSB1
(Power Down)
Output Disabled
Read
L
H
H
X
L
H
L
L
H
L
X
L
L
H
L
L
High Z
Dout
High Z
Dout
Din
High Z
Dout
Dout
High Z
Din
ICC
ICC
ICC
ICC
ICC
ICC
ICC
L
L
H
L
L
Write
X
X
Din
Din
X
H
Revision 2.5
April 2002
R0201-BS616UV2011
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BSI
BS616UV2011
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
RATING
UNITS
RANGE
Vcc
TEMPERATURE
Terminal Voltage with
-0.5 to
V
Respect to GND
Vcc+0.5
Commercial
Industrial
0 O C to +70O
-40 O C to +85O
C
1.8V ~ 3.6V
1.8V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
C
PT
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
IOUT
SYMBOL
CIN
PARAMETER
CONDITIONS
MAX. UNIT
Input
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
VIN=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
(1)
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
NAME
Vcc=2.0V
Vcc=3.0V
0.6
0.8
Guaranteed Input Low
IL
V
-0.5
--
--
V
V
(2)
Voltage
Vcc=2.0V
Vcc=3.0V
1.4
2.0
--
Guaranteed Input High
IH
V
Vcc+0.2
(2)
Voltage
IN
IIL
Input Leakage Current
Vcc = Max, V = 0V to Vcc
--
--
1
1
uA
uA
IH
IH
Vcc = Max, CE = V , or OE = V ,
IOL
Output Leakage Current
--
I/O
V
= 0V to Vcc
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 1mA
--
--
0.4
V
V
1.6
2.4
--
OH
VOH
Vcc = Min, I = -0.5mA
--
--
--
Vcc=2.0V
Vcc=3.0V
15
20
0.1
0.5
0.5
0.7
Operating Power Supply
Current
(3)
CC
IL
DQ
I
CE = V , I = 0mA, F = Fmax
mA
--
--
--
--
--
--
--
--
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
CCSB
IH
DQ
I
Standby Current ΓTTL
CE = V , I = 0mA
mA
uA
0.08
0.1
CE
Vcc-0.2V,
Њ
Њ
CCSB1
I
Standby CurrentΓCMOS
IN
IN
V
Vcc - 0.2V or V
0.2V
Љ
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE Њ Vcc - 0.2V
ICCDR
Data Retention Current
--
0
0.05
0.5
uA
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
Revision 2.5
April 2002
R0201-BS616UV2011
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BSI
BS616UV2011
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1333
1333
5PF
MAY CHANGE
FROM L TO H
WILL BE
2V
2V
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
100PF
INCLUDING
INCLUDING
ANY CHANGE
PERMITTED
Ω
Ω
2000
2000
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
800
Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
BS616UV2011-70
MIN. TYP. MAX.
BS616UV2011-10
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
tAVAX
tAVQV
tELQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tGHQZ
tRC
tAA
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACS
Chip Select Access Time
(CE)
(LB,UB)
--
--
--
--
--
--
(1)
tBA
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
(CE)
(LB,UB)
10
10
10
0
0
0
15
15
15
0
0
0
--
--
35
35
30
--
--
40
40
35
(CE)
(LB,UB)
tAXOX
tOH
Output Disable to Address Change
10
--
--
15
--
--
ns
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; .tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
Revision 2.5
April 2002
R0201-BS616UV2011
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BSI
BS616UV2011
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
t
BA
LB,UB
(5)
t
CHZ
t
BE
t
BDO
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
(1,5)
(5) t ACS
CLZ
t
OHZ
t
t
CHZ
t
BA
LB,UB
D OUT
t
BE
t
BDO
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.5
April 2002
R0201-BS616UV2011
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BSI
BS616UV2011
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V )
WRITE CYCLE
JEDEC
PARAMETER
BS616UV2011-70
MIN. TYP. MAX.
BS616UV2011-10
UNIT
PARAMETER
DESCRIPTION
Write Cycle Time
MIN. TYP. MAX.
NAME
NAME
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWLQZ
tDVWH
tWHDX
tGHQZ
tWC
tCW
tAS
tAW
tWP
tWR
Chip Select to End of Write
Address Setup Time
--
--
Address Valid to End of Write
Write Pulse Width
70
35
0
--
100
50
0
--
--
--
Write recovery Time
(CE,WE)
(LB,UB)
--
--
(1)
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
30
0
--
40
0
--
tBW
30
--
40
--
tWHZ
tDW
tDH
30
0
40
0
--
--
0
30
0
40
tOHZ
tWHOX
tOW
End of Write to Output Active
5
--
--
10
--
--
ns
NOTE :
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
t
WR
(11)
CW
t
(5)
CE
t
BW
LB,UB
WE
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.5
April 2002
R0201-BS616UV2011
6
BSI
BS616UV2011
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
CE
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
t
WHZ
(7)
(8)
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 2.5
April 2002
R0201-BS616UV2011
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BSI
BS616UV2011
ORDERING INFORMATION
BS616UV2011 X X -- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
E: TSOP 2 - 44 PIN
T: TSOP 1 - 48 PIN
A: BGA - 48 PIN(6x8mm)
D: DICE
PACKAGE DIMENSIONS
TSOP2-44
Revision 2.5
April 2002
R0201-BS616UV2011
8
BSI
BS616UV2011
PACKAGE DIMENSIONS
UNIT
SYMBOL
HD
INCH
MM
A
0.0433̈́0.004
1.10̈́0.10
0.10̈́0.05
1.00̈́0.05
0.22̈́0.05
0.20̈́0.03
0.10 ~ 0.21
0.10 ~ 0.16
16.40̈́0.10
12.00̈́0.10
0.50̈́0.10
18.00̈́0.20
0.60̈́0.15
0.80̈́0.10
0.1 Max.
C
L
A1 0.004̈́0.002
A2 0.039̈́0.002
1
48
b
0.009̈́0.002
b1 0.008̈́0.001
0.004 ~ 0.008
c1 0.004 ~ 0.006
c
D
E
e
0.645̈́0.004
0.472̈́0.004
0.020̈́0.004
HD 0.708̈́0.008
0.0236̈́0.006
L
24
25
12̓(2x)
L1 0.0315̈́0.004
Seating Plane
y
y
Ӱ
0.004 Max.
0̓~ 8̓
"A"
0̓~ 8̓
D
GAUGE PLANE
A
A
24
25
SEATING PLANE
12̓(2x)
L
b
L1
WITH PLATING
"A" DETAIL VIEW
c
c1
BASE METAL
b1
SECTION A-A
48
1
TSOP1-48PIN
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
A16
NC
VSS
IO15
IO7
IO14
IO6
A8
IO13
IO5
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
9
10
IO12
IO4
Pkg Type :
37
VCC
IO11
IO3
13
48TSOP(I)-12x18mm
IO10
IO2
16
17
IO9
IO1
A6
IO8
A5
IO0
A4
/OE
VSS
/CE
A0
A3
27
25
A2
A1
24
Revision 2.5
April 2002
R0201-BS616UV2011
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BSI
BS616UV2011
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8)
Revision 2.5
April 2002
R0201-BS616UV2011
10
BSI
REVISION HISTORY
BS616UV2011
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ. Jun. 29, 2001
and Max.)
2.4
2.5
Modify CSP Pin Configuration Sep. 12, 2001
Pin number : E3
“ VSS ” rename to “ N.C. “
Modify some AC parameters
April,12,2002
Revision 2.5
April 2002
R0201-BS616UV2011
11
相关型号：
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