BS616UV4010EI [BSI]
Ultra Low Power/Voltage CMOS SRAM 256K X 16 bit; 超低功率/电压CMOS SRAM 256K ×16位
| 型号： | BS616UV4010EI |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 256K X 16 bit |
| 文件： | 总10页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
256K X 16 bit
BSI
BS616UV4010
DESCRIPTION
FEATURES
• Ultra low operation voltage : 1.8 ~ 3.6V
The BS616UV4010 is a high performance, Ultra low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.20uA and maximum access time of 70/100ns in 2.0V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
• Ultra low power consumption :
Vcc = 2.0V
Vcc = 3.0V
C-grade: 15mA (Max.) operating current
I-grade: 20mA (Max.) operating current
0.20uA (Typ.) CMOS standby current
C-grade: 20mA (Max.) operating current
I-grade: 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current
• High speed access time :
The BS616UV4010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
-70
-10
70ns (Max.) at Vcc = 2.0V
100ns (Max.) at Vcc = 2.0V
The BS616UV4010 is available in DICE form, JEDEC standard 44-pin
TSOP Type 2 package and 48-pin BGA package.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
Operating
(SICTCSAB1NDBY
(
ns )
OPERATING
Vcc
, Max )
( I CC , Max )
PRODUCT FAMILY
PKG TYPE
TEMPERATURE
RANGE
Vcc=
Vcc=
3.0V
Vcc=
Vcc=
3.0V
Vcc=2.0V
2.0V
1uA
2.0V
BS616UV4010DC
DICE
TSOP2-44
+0O C to +70O C
-40O C to +85OC
1.8V ~ 3.6V
1.8V ~ 3.6V
70 / 100
1.5uA
3uA
15mA
20mA
25mA
BS616UV4010EC
BS616UV4010BC
BS616UV4010DI
BS616UV4010EI
BGA-48-0810
DICE
70 / 100
2uA
20mA
TSOP2-44
BS616UV4010BI
BGA-48-0810
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A5
A6
3
A2
A7
4
A1
OE
5
A4
A3
A2
A0
UB
6
CE
LB
7
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
8
9
A1
Address
10
11
12
13
14
15
16
17
18
19
20
21
22
22
2048
A0
A17
A16
A15
A14
A13
A12
BS616UV4010EC
BS616UV4010EI
Input
Row
Memory Array
2048 x 2048
Buffer
Decoder
A17
A16
A15
A14
A13
A8
A9
A10
A11
A12
2048
Data
Input
Buffer
16
16
16
Column I/O
DQ0
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
128
Data
16
Output
Buffer
Column Decoder
DQ15
14
CE
WE
OE
UB
Control
Address Input Buffer
LB
A11 A10 A9 A8 A7
A6 A5
Vcc
Gnd
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS616UV4010
1
BSI
BS616UV4010
PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
Not selected
X
X
High Z
High Z
I
CCSB, ICCSB1
(Power Down)
Output Disabled
L
H
H
X
L
H
L
L
H
L
X
L
L
H
L
L
High Z
Dout
High Z
Dout
Din
High Z
Dout
Dout
High Z
Din
ICC
ICC
ICC
ICC
ICC
ICC
ICC
Read
L
L
H
L
L
Write
X
X
Din
Din
X
H
Revision 2.4
April 2002
R0201-BS616UV4010
2
BSI
BS616UV4010
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
SYMBOL
PARAMETER
RATING
UNITS
RANGE
Vcc
TEMPERATURE
Terminal Voltage with
-0.5 to
0 O C to +70 O C
1.8V ~ 3.6V
1.8V ~ 3.6V
V
TERM
V
Commercial
Industrial
Respect to GND
Vcc+0.5
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
-40 O C to +85 O C
BIAS
T
T
P
STG
T
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER CONDITIONS MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
VIN=0V
I/O
6
8
pF
Capacitance
Input/Output
Capacitance
DQ
C
V
=0V
pF
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
(1)
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP. MAX.
NAME
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Guaranteed Input Low
0.6
IL
V
-0.5
--
V
(2)
Voltage
0.8
Guaranteed Input High
1.4
2.0
--
Vcc+0.2
IH
V
--
--
V
(2)
Voltage
IN
IIL
OL
Input Leakage Current Vcc = Max, V = 0V to Vcc
1
1
uA
IH
Vcc = Max, CE = VIH , or OE,= V
Output Leakage Current
I
--
--
uA
V
I/O = 0V to Vcc
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 1mA
Vcc = Min, IOH = -0.5mA
--
--
--
--
0.4
--
V
V
1.6
2.4
VOH
ICC
Operating Power Supply
Current
15
20
0.5
1
1
1.5
Fmax(3)
CE=VIL ,IDQ= 0mA, F =
--
mA
Vcc=2.0V
CCSB
IH
DQ
I
Standby Current-TTL
CE = V , I = 0mA
--
--
mA
uA
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
0.2
0.25
CE Vcc-0.2V,
Њ
Њ
ICCSB1
Standby Current-CMOS
--
V
IN
Vcc - 0.2V or V 0.2V
IN Љ
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
UNITS
CE
Vcc - 0.2V
Њ
Њ
VDR
Vcc for Data Retention
1.5
--
--
V
IN
IN
V
Vcc - 0.2V or V
0.2V
Љ
Љ
CE
Vcc - 0.2V
Vcc - 0.2V or V
Њ
Њ
ICCDR
Data Retention Current
--
0
0.1
1
uA
IN
IN
V
0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
Revision 2.4
April 2002
R0201-BS616UV4010
3
BSI
BS616UV4010
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1333
1333
5PF
2V
2V
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
100PF
DON T CARE:
CHANGE :
STATE
INCLUDING
INCLUDING
Ω
Ω
2000
2000
ANY CHANGE
PERMITTED
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
800
Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
BS616UV4010-70
MIN. TYP. MAX.
BS616UV4010-10
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
tAVAX
tAVQV
tELQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tRC
tAA
70
--
--
--
--
--
--
--
--
--
--
--
--
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
35
35
--
tACS
Chip Select Access Time
(CE)
--
--
(1)
tBA
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(LB,UB)
--
--
--
--
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
(CE)
10
10
10
0
15
15
15
0
(LB,UB)
--
--
35
35
30
--
--
40
40
35
(CE)
(LB,UB)
0
0
0
0
tGHQZ
tAXOX
tOH
Output Disable to Address Change
10
--
--
15
--
--
ns
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
Revision 2.4
April 2002
R0201-BS616UV4010
4
BSI
BS616UV4010
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
t
BA
LB,UB
(5)
t
CHZ
t
BE
t
BDO
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
(1,5)
(5) t ACS
CLZ
t
OHZ
t
t
CHZ
t
BA
LB,UB
D OUT
t
BE
t
BDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.4
April 2002
R0201-BS616UV4010
5
BSI
BS616UV4010
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V )
WRITE CYCLE
JEDEC
PARAMETER
BS616UV4010-70
MIN. TYP. MAX.
BS616UV4010-10
UNIT
PARAMETER
DESCRIPTION
Write Cycle Time
MIN. TYP. MAX.
NAME
NAME
tWC
tCW
tAS
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Setup Time
--
--
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR1
70
35
0
--
100
50
0
--
--
--
Write recovery Time
(CE,WE)
(LB,UB)
--
--
(1)
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
tBW
30
0
--
40
0
--
tWHZ
tDW
tDH
tWLQZ
tDVWH
tWHDX
tGHQZ
30
--
40
--
30
0
40
0
--
--
tOHZ
0
30
0
40
tOW
tWHOX
End of Write to Output Active
5
--
--
10
--
--
ns
NOTE :
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
t
WR
(11)
CW
t
(5)
CE
t
BW
LB,UB
WE
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.4
April 2002
R0201-BS616UV4010
6
BSI
BS616UV4010
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
CE
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
t
WHZ
(7)
(8)
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 2.4
April 2002
R0201-BS616UV4010
7
BSI
BS616UV4010
ORDERING INFORMATION
BS616UV4010 X X -- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
E: TSOP 2
B :BGA - 48 PIN(8x10mm)
D: DICE
PACKAGE DIMENSIONS
TSOP2-44
Revision 2.4
April 2002
R0201-BS616UV4010
8
BSI
BS616UV4010
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
48
D
10.0
E
8.0
D1
5.25
E1
3.75
e
0.75
SOLDER BALL
0.35̈́ 0.05
VIEW A
48 mini-BGA (8 x 10mm)
Revision 2.4
April 2002
R0201-BS616UV4010
9
BSI
REVISION HISTORY
BS616UV4010
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ. Jun. 29, 2001
and Max.)
2.4
Modify some AC parameters
April,10,2002
Revision 2.4
April 2002
R0201-BS616UV4010
10
相关型号：
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