BS616UV4020BC [BSI]
Ultra Low Power/Voltage CMOS SRAM 256K x 16 or 512K x 8 bit switchable; 超低功率/电压CMOS SRAM 256K ×16或512K ×8位切换
| 型号： | BS616UV4020BC |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 256K x 16 or 512K x 8 bit switchable |
| 文件： | 总11页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
256K x 16 or 512K x 8 bit switchable
BSI
BS616UV4020
FEATURES
DESCRIPTION
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
The BS616UV4020 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits or
524,288 bytes by 8 bits selectable by CIO pin and operates from a
wide range of 1.8V to 3.6V supply voltage.
Vcc = 2.0V C-grade: 15mA (Max.) operating current
I-grade : 20mA (Max.) operating current
0.2uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.2uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW
output enable(OE) and three-state output drivers.
• High speed access time :
-70
-10
70ns (Max.) at Vcc=2.0V
100ns (Max.) at Vcc=2.0V
The BS616UV4020 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
•Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616UV4020 is available in DICE form and 48-pin BGA type.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
STANDBY
Operating
OPERATING
(ns)
PRODUCT FAMILY
Vcc RANGE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
Vcc=3V
Vcc=2V
Vcc=2V Vcc=3V
Vcc=2V
BS616UV4020DC
BS616UV4020BC
BS616UV4020DI
BS616UV4020BI
DICE
+0O C to +70O C
1.8V ~ 3.6V
1.8V ~ 3.6V
70 / 100
70 / 100
1uA
2uA
1.5uA 15mA
3uA 20mA
20mA
BGA-48-0810
DICE
-40O C to +85O
C
25mA
BGA-48-0810
BLOCK DIAGRAM
PIN CONFIGURATION
A15
A14
A13
A12
A11
A10
A9
Address
Input
22
2048
Row
Decoder
Memory Array
2048 x 2048
Buffer
A8
A17
A7
A6
2048
Data
16(8)
16(8)
Column I/O
Input
D0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16(8)
16(8)
128(256)
Data
Output
Buffer
Column Decoder
D15
CE1
CE2
14(16)
WE
OE
UB
Control
Address Input Buffer
LB
CIO
A16 A0 A1 A2 A3
A4 A5
(SAE)
Vdd
Vss
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS616UV4020
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BSI
BS616UV4020
PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
SAE Address Input
This address input incorporates with the above 18 address inputs select one of the
524,288 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 262,144 x 16-bit words configuration
is selected if CIO is HIGH. 524,288 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read
from or write to the device. If either chip enable is not active, the device is deselected
and is in a standby power mode. The DQ pins will be in the high impedance state
when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
Revision 2.4
R0201-BS616UV4020
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April 2002
BSI
BS616UV4020
TRUTH TABLE
MODE
CE1 CE2
OE
WE
CIO
LB
UB
SAE
D0~7
D8~15
VCC Current
H
X
X
L
X
X
X
X
Fully Standby
Output Disable
X
H
X
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
ICCSB, ICCSB1
L
H
X
X
ICC
L
H
L
H
L
L
Dout
High-Z
Dout
High-Z
Dout
Read from SRAM
( WORD mode )
L
H
L
X
H
L
H
H
X
X
ICC
Dout
L
H
Din
X
Write to SRAM
( WORD mode )
L
H
ICC
H
L
L
L
X
Din
Din
Din
Read from SRAM
( BYTE Mode )
Write to SRAM
( BYTE Mode )
L
L
H
H
L
X
H
L
L
L
X
X
X
X
A-1
A-1
Dout
Din
High-Z
X
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
RATING
UNITS
AMBIENT
TEMPERATURE
0 O C to +70 O
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
V
Vcc+0.5
Commercial
Industrial
C
1.8V ~ 3.6V
1.8V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
-40 O C to +85O
C
PT
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
IOUT
SYMBOL
PARAMETER CONDITIONS MAX.
UNIT
Input
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
CIN
VIN=0V
I/O
6
8
pF
Capacitance
Input/Output
Capacitance
DQ
C
V
=0V
pF
1. This parameter is guaranteed and not tested.
Revision 2.4
April 2002
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BS616UV4020
DC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC)
PARAMETER
(1)
PARAMETER
TEST CONDITIONS
MIN.
TYP.
--
MAX.
UNITS
NAME
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
-0.5
-0.5
1.4
0.6
Guaranteed Input Low
VIL
V
V
Voltage(2)
0.8
--
--
Vcc+0.2
Vcc+0.2
Guaranteed Input High
Voltage(2)
VIH
IIL
2.0
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
IH
IL
Vcc = Max, CE1 = V or CE2=V
OL
I
Output Leakage Current
--
1
uA
or OE = VIH, VI/O = 0V to Vcc
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
--
--
--
--
--
--
--
--
--
0.4
0.4
--
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 1mA
V
V
1.6
2.4
VOH
ICC
Vcc = Min, IOH = -0.5mA
--
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
--
--
--
15
IL
IH
Operating Power Supply Vcc = Max, CE1= V , CE2=V
mA
mA
(3)
DQ
Current
I
= 0mA, F = Fmax
20
0.6
Vcc = Max, CE1 = VIH or CE2=VIL
ICCSB
Standby Current - TTL
DQ
I
= 0mA
Vcc=3.0V
Vcc=2.0V
--
--
--
1
1
0.2
Vcc = Max, CE1ЊVcc-0.2V or
Standby Current -CMOS CE2Љ0.2V ;VINЊ Vcc - 0.2V or
ICCSB1
uA
IN
Љ
V
0.2V
Vcc=3.0V
--
0.25
1.5
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
Revision 2.4
April 2002
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BS616UV4020
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
UNITS
CE1
VIN
Vcc - 0.2V or CE2
0.2V ;
Њ
Љ
0.2V
V
VDR
Vcc for Data Retention
1.5
--
--
Vcc - 0.2V or VIN
Њ
Љ
CE1
VIN
Vcc - 0.2V or CE2
0.2V
Њ
Љ
0.2V
ICCDR
Data Retention Current
--
0
0.1
1
uA
Vcc - 0.2V or VIN
Њ
Љ
Chip Deselect to Data
Retention Time
tCDR
--
--
--
--
ns
ns
See Retention Waveform
(2)
tR
Operation Recovery Time
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR Њ 1.5V
V
Vcc
Vcc
t
Vcc
CE1
R
t
CDR
CE1 Њ Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR Њ 1.5V
V
Vcc
Vcc
t
Vcc
CE2
R
t
CDR
CE2 Љ 0.2V
VIL
VIL
Revision 2.4
April 2002
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BS616UV4020
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
Ω
Ω
1333
1333
5PF
CHANGE
2V
OUTPUT
2V
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
ANY CHANGE
PERMITTED
100PF
UNKNOWN
INCLUDING
INCLUDING
Ω
Ω
2000
2000
JIG AND
SCOPE
JIG AND
SCOPE
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
800
Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc=2.0V )
READ CYCLE
JEDEC
BS616UV4020-70
BS616UV4020-10
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
UNIT
PARAMETER PARAMETER
NAME
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVQV
tE1LQV
tE2LQV
tBA
tRC
70
70
70
70
35
35
10
10
10
100
100
100
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACS1
tACS2
(CE1)
(CE2)
(LB,UB)
(1)
tBA
tGLQV
tE1LQX
tBE
tOE
50
tCLZ
tBE
(CE2,CE1)
(LB,UB)
15
15
15
tGLQX
tE1HQZ
tBDO
tOLZ
tCHZ
tBDO
tOHZ
(CE2,CE1)
(LB,UB)
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
0
0
0
35
35
30
0
0
0
40
40
35
tGHQZ
10
15
ns
tOH
tAXQX
Output Disable to Output Address Change
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
Revision 2.4
April 2002
R0201-BS616UV4020
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BSI
BS616UV4020
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
DOUT
READ CYCLE2 (1,3,4)
CE2
t
t
ACS2
ACS1
CE1
(5)
CHZ
(5)
CLZ
t
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
CE2
CE1
t
ACS2
t
OLZ
(5)
t
ACS1
t
t
OHZ
(1,5)
CHZ
(5)
CLZ
t
LB,UB
D OUT
t
BE
t
BDO
t
BA
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.4
April 2002
R0201-BS616UV4020
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BSI
BS616UV4020
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc=2.0V )
WRITE CYCLE
JEDEC
BS616UV4020-70
BS616UV4020-10
UNIT
MIN. TYP. MAX.
PARAMETER PARAMETER
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Set up Time
NAME
NAME
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWC
tCW
tAS
100
100
0
100
50
0
40
0
70
70
0
70
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tWP
tWR
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
(CE2, CE1, WE)
(1)
tBW
tWHZ
tDW
tDH
Data Byte Control to End of Write (LB,UB) 30
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
Write to Output in High Z
0
30
0
0
5
40
40
30
30
40
0
0
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
tOHZ
tOW
10
NOTE :
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle .
tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle .
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(5)
CE2
(11)
CW
t
(5)
CE1
t
BW
(5)
LB,UB
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
DIN
Revision 2.4
April 2002
R0201-BS616UV4020
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BSI
BS616UV4020
WRITE CYCLE2 (1,6)
t
WC
ADDRESS
CE2
(11)
CW
t
(5)
(5)
CE1
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
WHZ
(7)
(8)
t
D OUT
t
DW
(8,9)
t
DH
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
Revision 2.4
April 2002
R0201-BS616UV4020
9
BSI
BS616UV4020
ORDERING INFORMATION
BS616UV4020 X X -- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
B :BGA - 48 PIN(8x10mm)
D :DICE
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
48
D
10.0
E
8.0
D1
5.25
E1
3.75
e
0.75
SOLDER BALL
0.35̈́ 0.05
VIEW A
48 mini-BGA (8 x 10mm)
Revision 2.4
April 2002
R0201-BS616UV4020
10
BSI
REVISION HISTORY
BS616UV4020
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ. Jun. 29, 2001
and Max.)
2.4
Modify some AC parameters
April,11,2002
Revision 2.4
April 2002
R0201-BS616UV4020
11
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