BS62LV1023STC70 [BSI]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32;
| 型号： | BS62LV1023STC70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
BSI
BS62LV1023
DESCRIPTION
FEATURES
The BS62LV1023 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1023 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1023 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4
mm STSOP and 8mmx20mm TSOP.
• Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
STANDBY
Operating
(ICC, Max)
PKG TYPE
(ICCSB1, Max)
Vcc= 3.0V
Vcc=3.0V
Vcc=3.0V
BS62LV1023SC
BS62LV1023TC
BS62LV1023STC
BS62LV1023PC
BS62LV1023JC
BS62LV1023DC
BS62LV1023SI
BS62LV1023TI
BS62LV1023STI
BS62LV1023PI
BS62LV1023JI
BS62LV1023DI
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
+0 O C to +70 O
C
C
2.4V ~ 3.6V
2.4V ~ 3.6V
70
1.0uA
20mA
-40 O C to +85 O
70
1.5uA
25mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
NC
A16
A14
A12
A7
1
VCC
32
2
A15
CE2
WE
A13
A8
31
A6
A7
A12
A14
A16
A15
A13
A8
3
30
4
29
5
Address
28
27
Memory Array
1024 x 1024
20
1024
A6
6
Row
Decoder
Input
A5
7
A9
BS62LV1023SC 26
A4
8
BS62LV1023SI
BS62LV1023PC
BS62LV1023PI
BS62LV1023JC
BS62LV1023JI
A11
OE
25
24
23
22
21
20
19
18
17
Buffer
A3
9
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A9
A11
A1
A0
DQ0
DQ1
DQ2
GND
1024
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
8
8
Data
Output
Buffer
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
OE
128
Column Decoder
14
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
BS62LV1023TC
CE2
CE1
WE
BS62LV1023STC
BS62LV1023TI
BS62LV1023STI
Control
Address Input Buffer
9
10
11
12
13
14
15
16
OE
Vdd
Gnd
A5 A4 A3 A2 A1 A0 A10
A6
A5
A4
A1
A2
A3
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.3
Jan. 2004
R0201-BS62LV1023
1
BSI
BS62LV1023
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
CE1
H
CE2
X
OE
X
I/O OPERATION
High Z
Vcc CURRENT
Not selected
(Power Down)
ICCSB, ICCSB1
X
X
L
X
Output Disabled
Read
H
L
H
H
L
High Z
ICC
ICC
ICC
OUT
H
L
H
D
IN
Write
L
L
H
X
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
TEMPERATURE
0 O C to +70O
SYMBOL
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
UNITS
RANGE
Vcc
V
TERM
V
Commercial
Industrial
C
2.4V ~ 3.6V
2.4V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
BIAS
T
-40 O C to +85O
C
STG
T
T
P
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
IN
PARAMETER
CONDITIONS
IN
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
C
V
=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
Revision 2.3
Jan. 2004
R0201-BS62LV1023
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BSI
BS62LV1023
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
-0.5 -- 0.8
NAME
Guaranteed Input Low
Voltage(2)
Vcc=3.0V
Vcc=3.0V
IL
V
V
Guaranteed Input High
IH
V
2.0
--
--
--
Vcc+0.2
1
V
Voltage(2)
IL
IN
I
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
uA
IH
IL,
Vcc = Max, CE1= V , CE2= V or
ILO
--
--
1
uA
IH
I/O
OE = V , V = 0V to Vcc
Vcc = Max, I = 2mA
Vcc = Min, I = -1mA
Vcc=3.0V
Vcc=3.0V
OL
OL
V
Output Low Voltage
Output High Voltage
--
--
--
0.4
--
V
V
OH
OH
V
2.4
IL
IH
(3)
Operating Power Supply CE1 = V , or CE2 = V ,
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
ICC
--
--
--
--
--
20
1
mA
mA
uA
DQ
I
Current
= 0mA, F = Fmax
IH
IL
CE1 = V , or CE2 = V ,
ICCSB
Standby Current-TTL
DQ
I
= 0mA
CE1≧Vcc-0.2V or CE2≦0.2V,
VIN Vcc-0.2V or V 0.2V
CCSB1
I
Standby Current-CMOS
0.02
1.0
≧
≦
IN
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
ICCDR
Data Retention Current
--
0
0.02
0.3
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
CE1
t
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR ≧ 1.5V
V
Vcc
Vcc
Vcc
t
R
t
CDR
CE2 ≦ 0.2V
VIL
VIL
CE2
Revision 2.3
Jan. 2004
R0201-BS62LV1023
3
BSI
BS62LV1023
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Vcc/0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
AC TEST LOADS AND WAVEFORMS
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Ω
Ω
1269
1269
3.3V
3.3V
OUTPUT
OUTPUT
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
100PF
5PF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Ω
Ω
1404
1404
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
MIN. TYP. MAX.
PARAMETER
DESCRIPTION
Read Cycle Time
UNIT
NAME
tAVAX
tAVQV
tE1LQV
tE2HOV
tGLQV
tRC
70
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
70
70
70
50
--
tACS1
tACS2
tOE
Chip Select Access Time
(CE1)
(CE2)
--
Chip Select Access Time
--
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
tE1LQX
tE2HOX
tGLQX
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
(CE1)
(CE2)
10
10
10
0
--
--
tE1HQZ
tE2HQZ
tGHQZ
(CE1)
(CE2)
40
40
35
0
0
--
--
ns
ns
tAXOX
tOH
Output Disable to Output Address Change
10
--
Revision 2.3
Jan. 2004
R0201-BS62LV1023
4
BSI
BS62LV1023
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
t
t
ACS1
ACS2
CE2
(5)
CHZ2
t
CHZ1,
t
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
t
OLZ
CE1
(5)
t
ACS1
t
t
OHZ
(1,5)
(5)
t
t
CLZ1
CHZ1
CE2
t
ACS2
(2,5)
CHZ2
t
(5)
CLZ2
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL
.
±
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.3
Jan. 2004
R0201-BS62LV1023
5
BSI
BS62LV1023
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Write Cycle Time
UNIT
tAVAX
t E1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tE2LAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tWC
tCW
tAS
70
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set up Time
70
0
--
--
tAW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
70
50
0
--
--
Write Recovery Time
(CE1 , WE)
(CE2)
--
Write Recovery Time
0
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
0
30
--
30
0
--
tOHZ
tOW
0
30
--
5
WRITE CYCLE1 (1)
ADDRESS
t
WC
(3)
t
WR1
OE
(11)
t
CW
(5)
(5)
CE1
CE2
WE
(11)
(2)
t
t
CW
WP
t
WR2
t
AW
(3)
t
AS
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.3
Jan. 2004
R0201-BS62LV1023
6
BSI
BS62LV1023
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE1
(11)
CW
CE2
t
t
WR2
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
t
t
OW
DH
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
±
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 2.3
Jan. 2004
R0201-BS62LV1023
7
BSI
BS62LV1023
ORDERING INFORMATION
BS62LV1023 X X Z Y Y
SPEED
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
BASE METAL
b1
SECTION A-A
SOP -32
Revision 2.3
Jan. 2004
R0201-BS62LV1023
8
BSI
BS62LV1023
PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
Revision 2.3
Jan. 2004
R0201-BS62LV1023
9
BSI
BS62LV1023
PACKAGE DIMENSIONS (continued)
PDIP - 32
SOJ - 32
Revision 2.3
Jan. 2004
R0201-BS62LV1023
10
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