BS62LV1024TC [BSI]
Very Low Power/Voltage CMOS SRAM 128K X 8 bit; 非常低的功率/电压CMOS SRAM 128K ×8位
| 型号： | BS62LV1024TC |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 128K X 8 bit |
| 文件： | 总11页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
BSI
BS62LV1024
DESCRIPTION
FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
The BS62LV1024 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
The BS62LV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS62LV1024 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4mm
STSOP and 8mmx20mm TSOP.
• Data retention supply voltage as low as 1.5V
• EPasRyOexDpaUnCsiTonFwAithMCILE2Y, CE1, and OE options
P O W E R D IS SIPATIO N
S P E E D
P R O D U C T
FAM ILY
O P E R ATIN G
V cc
S tandb y
O perating
(ns)
P K G TY P E
(Icc, M ax)
TE M P E R ATU R E
R AN G E
(IccS B 1, M ax)
V cc=3V
V cc=5V
V cc=3V V cc=5V V cc=3V
B S 62LV 1024S C
B S 62LV 1024TC
B S 62LV 1024S TC
B S 62LV 1024P C
B S 62LV 1024JC
B S 62LV 1024D C
B S 62LV 1024SI
B S 62LV 1024TI
B S 62LV 1024S TI
B S 62LV 1024PI
B S 62LV 1024JI
B S 62LV 1024D I
S O P -32
TS O P -32
S TS O P -32
P D IP -32
S O J-32
D IC E
S O P -32
TS O P -32
S TS O P -32
P D IP -32
S O J-32
D IC E
+0O C to +70 O C 2.4V ~ 5.5V
70
70
3.0uA
1.0uA
1.5uA
35m A
20m A
-40O C to +85 O C 2.4V ~ 5.5V
5.0uA
40m A
25m A
PIN CONFIGURATIONS
BLOCK DIAGRAM
NC
A16
A14
A12
A7
1
VCC
A15
CE2
WE
A13
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
A6
A7
3
4
A12
5
Address
Memory Array
1024 x 1024
A14
20
1024
A6
6
BS62LV1024SC
BS62LV1024SI
BS62LV1024PC
BS62LV1024PI
BS62LV1024JC
BS62LV1024JI
Row
A16
A15
A13
A8
Input
A5
7
A9
A4
8
A11
OE
Decoder
Buffer
A3
9
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A9
A1
A11
A0
DQ0
DQ1
DQ2
GND
1024
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Column I/O
8
Input
Buffer
Write Driver
Sense Amp
8
8
Data
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
OE
128
Column Decoder
14
Output
Buffer
2
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
3
A8
4
A13
WE
CE2
A15
VCC
NC
5
6
BS62LV1024TC
CE2
CE1
WE
OE
Vdd
Gnd
7
BS62LV1024STC
BS62LV1024TI
BS62LV1024STI
8
Control
Address Input Buffer
9
10
11
12
13
14
15
16
A16
A14
A12
A7
A5 A4 A3 A2 A1 A0 A10
A6
A1
A5
A2
A4
A3
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.2
April 2001
R0201-BS62LV1024
1
BSI
BS62LV1024
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
X
CE1
H
X
CE2
X
L
OE
X
X
I/O OPERATION
High Z
Vcc CURRENT
Not selected
ICCSB, ICCSB1
(Power Down)
Output Disabled
Read
H
H
L
L
L
L
H
H
H
H
L
X
High Z
ICC
ICC
ICC
OUT
D
IN
Write
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
TEMPERATURE
0 O C to +70 O
-40 O C to +85O
SYMBOL
PARAMETER
RATING
UNITS
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
V
TERM
BIAS
STG
T
V
T
T
P
Vcc+0.5
Commercial
Industrial
C
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
IN
C
IN
V
=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
Revision 2.2
April 2001
R0201-BS62LV1024
2
BSI
BS62LV1024
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP.(1) MAX.
NAME
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Guaranteed Input Low
VIL
-0.5
--
0.8
V
Voltage(2)
Guaranteed Input High
Voltage(2)
2.0
2.2
--
VIH
IIL
--
--
--
Vcc+0.2
V
IN
Input Leakage Current
Vcc = Max, V = 0V to Vcc
1
1
uA
uA
IH
IL,
Vcc = Max, CE1= V , CE2= V or
IOL
Output Leakage Current
--
IH
I/O
OE = V , V = 0V to Vcc
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
OL
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2mA
--
--
--
0.4
--
V
V
OH
Vcc = Min, I = -1mA
2.4
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
--
--
--
--
--
--
--
--
--
--
0.02
0.4
20
35
1
2
1
IL
IH
Operating Power Supply CE1 = V , or CE2 = V ,
ICC
mA
mA
uA
(3)
DQ
Current
I
= 0mA, F = Fmax
IH
IL
(3)
CE1 = V , or CE2 = V ,
ICCSB
ICCSB1
Standby Current-TTL
DQ
I
= 0mA, F = Fmax
CE1ЊVcc-0.2V, CE2Љ0.2V,
Standby Current-CMOS
IN
Њ
V
IN
Љ
Vcc-0.2V or V 0.2V
3
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.(1) MAX.
UNITS
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
ICCDR
Data Retention Current
--
0
0.02
0.3
uA
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
VDR Њ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
CE2 Љ 0.2V
VIL
VIL
CE2
Revision 2.2
April 2001
R0201-BS62LV1024
3
BSI
BS62LV1024
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
Ω
Ω
1269
1269
CHANGE
3.3V
OUTPUT
3.3V
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
ANY CHANGE
PERMITTED
100PF
5PF
INCLUDING
INCLUDING
UNKNOWN
Ω
Ω
1404
1404
JIG AND
SCOPE
JIG AND
SCOPE
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V )
READ CYCLE
JEDEC
PARAMETER
BS62LV1024-70
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
MIN. TYP. MAX.
NAME
tAVAX
tAVQV
tE1LQV
tE2HOV
tGLQV
tE1LQX
tE2HOX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
tRC
t AA
t ACS1
t ACS2
tOE
t CLZ1
t CLZ2
tOLZ
t CHZ1
t CHZ2
tOHZ
70
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
--
--
70
70
70
50
--
Chip Select Access Time
(CE1)
(CE2)
Chip Select Access Time
--
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
(CE1)
(CE2)
10
10
10
0
--
--
(CE1)
(CE2)
40
40
35
0
0
--
--
ns
ns
tAXOX
tOH
Output Disable to Address Change
10
--
Revision 2.2
April 2001
R0201-BS62LV1024
4
BSI
BS62LV1024
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
t
t
ACS1
ACS2
CE2
(5)
CHZ2
t
CHZ1,
t
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
t
OLZ
CE1
(5)
t
ACS1
t
OHZ
(1,5)
CHZ1
(5)
CLZ1
t
t
t
CE2
t
(5)
ACS2
(2,5)
CHZ2
t
CLZ2
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.2
April 2001
R0201-BS62LV1024
5
BSI
BS62LV1024
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V )
WRITE CYCLE
JEDEC
PARAMETER
BS62LV1024-70
MIN. TYP. MAX.
DESCRIPTION
UNIT
PARAMETER
NAME
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tE2LAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tWC
Write Cycle Time
70
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tAS
Chip Select to End of Write
Address Set up Time
70
0
--
--
tAW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
70
50
0
--
--
Write Recovery Time
(CE1 , WE)
(CE2)
--
Write Recovery Time
0
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
0
30
--
30
0
--
tOHZ
tOW
0
30
--
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
t
t
WR1
(11)
t
CW
(5)
CE1
(5)
(11)
(2)
CE2
t
t
CW
WP
WR2
t
AW
(3)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
D IN
Revision 2.2
April 2001
R0201-BS62LV1024
6
BSI
BS62LV1024
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE1
(11)
CW
CE2
t
t
WR2
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 2.2
April 2001
R0201-BS62LV1024
7
BSI
BS62LV1024
ORDERING INFORMATION
BS62LV1024
X X ˀˀ Y Y
SPEED
70: 70ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
BASE METAL
b1
SECTION A-A
SOP -32
Revision 2.2
April 2001
R0201-BS62LV1024
8
BSI
BS62LV1024
PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
Revision 2.2
April 2001
R0201-BS62LV1024
9
BSI
BS62LV1024
PACKAGE DIMENSIONS (continued)
PDIP - 32
SOJ - 32
Revision 2.2
April 2001
R0201-BS62LV1024
10
BSI
BS62LV1024
REVISION HISTORY
Revision
Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
Revision 2.2
April 2001
R0201-BS62LV1024
11
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