BS62LV1603ECP70 [BSI]
Very Low Power/Voltage CMOS SRAM 2M X 8 bit; 非常低的功率/电压CMOS SRAM 2M ×8位
| 型号： | BS62LV1603ECP70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 2M X 8 bit |
| 文件： | 总9页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
2M X 8 bit
BSI
BS62LV1603
FEATURES
GENERAL DESCRIPTION
• Vcc operation voltage : 2.7V ~ 3.6V
• Very low power consumption :
The BS62LV1603 is a high performance , very low power CMOS Static
Random Access Memory organized as 2048K words by 8 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
3.0uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
Vcc = 3.0V C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns
70ns
The BS62LV1603 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1603 is available in 48B BGA and 44L TSOP2 packages.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
Vcc=3V
70ns
Vcc=3V
55ns
55ns : 3.0~3.6V
70ns : 2.7~3.6V
Vcc=3V
10uA
BS62LV1603EC
BS62LV1603FC
BS62LV1603EI
BS62LV1603FI
TSOP2-44
BGA-48-0912
TSOP2-44
+0O C to +70OC 2.7V ~ 3.6V
-40OC to +85OC 2.7V ~ 3.6V
55 / 70
55 / 70
45mA
46mA
36mA
20uA
37mA
BGA-48-0912
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
A20
A5
A6
A7
OE
CE2
A8
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A20
A13
A17
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
BS62LV1603EC
BS62LV1603EI
A15
Address
Memory Array
A18
A16
A14
A12
A7
24
4096
Row
Input
4096 X 4096
Decoder
NC
A9
Buffer
WE
A19
A18
A17
A16
A15
18
19
20
21
A6
A5
A4
A10
A11
A12
A13
A14
22
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
1
2
3
4
5
6
8
Column I/O
Write Driver
Sense Amp
A
B
C
D
E
F
OE
A0
A1
A2
CE2
NC
NC
NC
8
8
Data
Output
Buffer
NC
NC
A3
A5
A4
CE1
NC
512
A6
D0
D4
Column Decoder
18
VSS
A17
VCC
A7
VCC
VSS
D1
D2
D5
D6
CE1
CE2
WE
OE
Control
A16
A15
A13
A10
VCC
D3
Address Input Buffer
D7
NC
NC
NC
WE
A11
A14
A12
A9
Vdd
Gnd
A11A9 A8 A3 A2 A1 A0A10 A19
A20
G
H
NC
A18
A8
A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
Jan. 2004
R0201-BS62LV1603
1
BSI
BS62LV1603
PIN DESCRIPTIONS
Name
Function
A0-A20 Address Input
These 21 address inputs select one of the 2048K x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
CE1
H
CE2
X
OE
X
I/O OPERATION
High Z
Vcc CURRENT
Not selected
(Power Down)
I
CCSB, ICCSB1
X
X
L
X
Output Disabled
Read
H
L
H
H
L
High Z
ICC
ICC
ICC
OUT
H
L
H
D
IN
Write
L
L
H
X
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
UNITS
AMBIENT
TEMPERATURE
0 O C to +70 O
RANGE
Vcc
V
TERM
BIAS
STG
T
V
T
T
P
Commercial
Industrial
C
2.7V ~ 3.6V
2.7V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
O C
W
-40 O C to +85O
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
VIN=0V
10
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
12
pF
1. This parameter is guaranteed and not 100% tested.
Revision 1.1
Jan. 2004
R0201-BS62LV1603
2
BSI
BS62LV1603
DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
NAME
Guaranteed Input Low
Voltage(3)
Vcc=3V
Vcc=3V
IL
V
-0.5
--
0.8
V
Guaranteed Input High
Voltage(3)
IH
V
2.0
--
--
--
--
Vcc+0.3
V
IL
IN
I
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
1
1
uA
uA
IH
IL
Vcc = Max, CE1 = V or CE2 = V or
LO
I
--
IH
I/O
OE = V , V = 0V to Vcc
Vcc=3V
Vcc=3V
Vcc=3V
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2mA
--
--
--
0.4
--
V
V
OH
OH
V
Vcc = Min, I = -1mA
2.4
55ns
70ns
--
--
--
--
46
37
IL
IH,
Operating Power Supply CE1= V , CE2= V
(4)
CC
I
mA
(2)
DQ
Current
I
= 0mA, F = Fmax
Vcc=3V
Vcc=3V
CCSB
IH
IL, DQ
I
Standby Current-TTL
CE1 = V or CE2= V I = 0mA
--
--
1.3
mA
uA
CE1≧Vcc-0.2V or CE2≦0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(5)
CCSB1
I
Standby Current-CMOS
--
3
20
1. Typical characteristics are at TA = 25oC.
2. Fmax = 1/tRC .
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc_Max. is 45mA(@55ns) / 36mA(@70ns) during 0~70oC operation.
5. IccsB1 is 10uA at Vcc=3.0V and TA=70oC.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.(1) MAX.
UNITS
CE1≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
5
V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(3)
ICCDR
Data Retention Current
--
0
1.5
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR(Max.) is 2.5uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
t
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR ≧ 1.5V
V
Vcc
Vcc
Vcc
t
R
t
CDR
CE2 ≦ 0.2V
VIL
VIL
CE2
Revision 1.1
R0201-BS62LV1603
3
Jan.
2004
BSI
BS62LV1603
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
CYCLE TIME : 55ns
PARAMETER
NAME
Vcc=2.7~3.6V
Vcc=3.0~3.6V
DESCRIPTION
Read Cycle Time
UNIT
MIN. TYP. MAX.
MIN. TYP. MAX.
t
t
70
--
--
--
--
--
--
--
--
--
--
--
55
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
70
70
70
35
--
55
55
55
30
--
AVQV
AA
t
tE1LQV
tE2LQV
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
(CE1)
--
--
ACS1
t
(CE2)
--
--
ACS2
t
t
--
--
GLQV
OE
t
t
10
10
--
10
10
--
ELQX
CLZ
t
t
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
GLQX
OLZ
t
t
35
30
30
25
EHQZ
CHZ
t
t
--
--
GHQZ
OHZ
tAXOX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
Revision 1.1
R0201-BS62LV1603
4
Jan.
2004
BSI
BS62LV1603
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t
t
ACS2
ACS1
CE1
(5)
CHZ
(5)
CLZ
t
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
CE2
CE1
t
ACS2
t
OLZ
(5)
t
ACS1
t
OHZ
(5)
CLZ
(1,5)
CHZ
t
t
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
.
Revision 1.1
Jan. 2004
R0201-BS62LV1603
5
BSI
BS62LV1603
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
Vcc=2.7~3.6V
CYCLE TIME : 55ns
PARAMETER
NAME
Vcc=3.0~3.6V
DESCRIPTION
Write Cycle Time
UNIT
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tWC
tCW
tAS
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set up Time
--
--
tAVWH
tWLWH
tWHAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tAW
tWP
tWR
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
70
35
0
--
55
30
0
--
--
--
Write Recovery Time
(CE2,CE1 , WE)
--
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
--
30
--
--
25
--
30
0
25
0
--
--
tOHZ
tOW
Output Disable to Output in High Z
End of Write to Output Active
--
30
--
--
25
--
5
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(5)
CE2
(11)
CW
t
(5)
CE1
t
AW
(3)
t
WP
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 1.1
Jan. 2004
R0201-BS62LV1603
6
BSI
BS62LV1603
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
CE2
(11)
CW
t
(5)
CE1
t
WR
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
t
OW
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
Revision 1.1
Jan. 2004
R0201-BS62LV1603
7
BSI
BS62LV1603
ORDERING INFORMATION
BS62LV1603 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
E: TSOP2-44
F: BGA-48-0912
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
TSOP2-44
Revision 1.1
Jan. 2004
R0201-BS62LV1603
8
BSI
BS62LV1603
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
N
D
E
D1
E1
e
D1
48
12.0
9.0
5.25
3.75
0.75
3.375
SOLDER BALL 0.35±0.05
VIEW A
48 mini-BGA (9mm x 12mm)
Revision 1.1
Jan. 2004
R0201-BS62LV1603
9
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