BS62LV2000SCG70 [BSI]
Standard SRAM, 256KX8, 70ns, CMOS, PDSO32;![BS62LV2000SCG70](http://pdffile.icpdf.com/pdf2/p00229/img/icpdf/BS62LV2000SI_1345715_icpdf.jpg)
型号: | BS62LV2000SCG70 |
厂家: | ![]() |
描述: | Standard SRAM, 256KX8, 70ns, CMOS, PDSO32 静态存储器 光电二极管 内存集成电路 |
文件: | 总9页 (文件大小:324K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BSI
BS62LV2000
DESCRIPTION
FEATURES
The BS62LV2000 is a high performance , very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a wide range of 2.7V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.15uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
• Wide Vcc operation voltage : 2.7V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.15uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 40mA (Max.) operating current
I- grade : 45mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
The BS62LV2000 has an automatic power down feature , reducing the
power consumption significantly when chip is deselected.
-70
-10
70ns(Max.) at Vcc = 3.0V
100ns(Max.) at Vcc = 3.0V
The BS62LV2000 is available in the JEDEC standard 32 pin 450mil
Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
• All I/O pins are 3V/5V tolerant
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
(I , Max)
Operating
, Max)
PRODUCT
FAMILY
OPERATING
Vcc
PKG TYPE
CCSB1
CC
(I
TEMPERATURE
RANGE
Vcc=3V
Vcc=5V Vcc=3V Vcc=5V Vcc=3V
BS62LV2000TC
BS62LV2000STC
BS62LV2000SC
BS62LV2000TI
BS62LV2000STI
BS62LV2000SI
TSOP 32
-
OC
OC to +70
2.7V ~ 5.5V 70 / 100
10uA
20uA
3uA
5uA
40mA
45mA
20mA
25mA
+0
STSOP 32
-
SOP 32
-
TSOP 32
-
O
O
-
40 C to +85 C 2.7V ~ 5.5V 70 / 100
STSOP 32
-
SOP 32
-
BLOCK DIAGRAM
PIN CONFIGURATIONS
1
A11
A9
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
3
A8
A13
A17
4
5
6
7
8
9
10
11
12
13
14
15
16
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A15
A16
A14
Address
Memory Array
1024 x 2048
20
1024
BS62LV2000TC
BS62LV2000STC
BS62LV2000TI
BS62LV2000STI
Row
Input
A12
A7
A6
A5
A4
Decoder
Buffer
A6
A5
A4
A1
A2
A3
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
8
Column I/O
Buffer
Write Driver
Sense Amp
A17
A16
A14
A12
A7
1
VCC
A15
CE2
WE
32
31
30
29
28
27
8
2
8
Data
3
256
Column Decoder
16
Output
Buffer
4
5
A13
A8
A6
6
A5
7
A9
26
25
24
23
22
21
20
19
18
17
BS62LV2001SC
BS62LV2001SI
A4
8
A11
OE
CE1
CE2
A3
9
Control
Address Input Buffer
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
WE
OE
A1
A0
Vdd
Gnd
DQ0
DQ1
DQ2
GND
A9 A8 A3 A2 A1 A0 A10
A11
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.4
Jan. 2004
R0201-BS62LV2000
1
BSI
BS62LV2000
PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
CE1
H
CE2
X
OE
X
I/O OPERATION
High Z
Vcc CURRENT
Not selected
(Power Down)
I
CCSB, ICCSB1
X
X
L
X
Output Disabled
Read
H
L
H
H
L
High Z
ICC
ICC
ICC
OUT
H
L
H
D
IN
Write
L
L
H
X
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
TEMPERATURE
0 O C to +70 O
SYMBOL
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
UNITS
RANGE
Vcc
V
TERM
V
Commercial
Industrial
C
2.7V ~ 5.5V
2.7V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
BIAS
T
-40 O C to +85O
C
STG
T
T
P
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
IN
V
=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
Revision 2.4
Jan. 2004
R0201-BS62LV2000
2
BSI
BS62LV2000
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
UNITS
NAME
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Guaranteed Input Low
Voltage(2)
IL
V
-0.5
--
0.8
V
Guaranteed Input High
2.0
2.2
IH
V
--
--
Vcc+0.2
1
V
Voltage(2)
IL
IN
I
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
--
uA
IH
IL
Vcc = Max, CE1 = V or CE2=V
LO
I
--
--
1
uA
IH
I/O
or OE = V , V = 0V to Vcc
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2mA
--
--
--
0.4
--
V
V
OH
OH
V
Vcc = Min, I = -1mA
2.4
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
--
--
--
--
--
--
--
20
40
1
Operating Power Supply Vcc = Max, CE1= VIL, CE2=VIH
Current
CC
I
mA
mA
I
DQ = 0mA, F = Fmax(3)
Vcc = Max, CE1 = VIH or
--
CCSB
IL
I
Standby Current-TTL
CE2=V
--
2
DQ
I
= 0mA
0.15
3
Vcc = Max, CE1≧Vcc-0.2V or
IN
≧
Vcc - 0.2V or
CE2≦0.2V ;V
IN≦0.2V
CCSB1
I
Standby Current-CMOS
uA
Vcc=5.0V
--
3
10
V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
ICCDR
Data Retention Current
--
0
0.01
1
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
CE1
t
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR ≧ 1.5V
V
Vcc
Vcc
Vcc
t
R
t
CDR
CE2 ≦ 0.2V
VIL
VIL
CE2
Revision 2.4
R0201-BS62LV2000
3
Jan.
2004
BSI
BS62LV2000
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Vcc/0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
AC TEST LOADS AND WAVEFORMS
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Ω
Ω
1269
1269
3.3V
3.3V
OUTPUT
OUTPUT
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
100PF
5PF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Ω
Ω
1404
1404
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
MIN. TYP. MAX.
CYCLE TIME : 100ns
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
tAVAX
tAVQV
tE1LQV
tE2HOV
tGLQV
tE1LQX
tE2HOX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
tRC
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACS1
tACS2
tOE
Chip Select Access Time
(CE1)
(CE2)
--
--
Chip Select Access Time
--
--
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
tCLZ1
tCLZ2
tOLZ
(CE1)
(CE2)
10
10
10
0
15
15
15
0
--
--
--
--
tCHZ1
tCHZ2
tOHZ
(CE1)
(CE2)
35
35
30
40
40
35
0
0
0
0
tAXOX
tOH
Output Disable to Output Address Change
10
--
--
15
--
--
ns
Revision 2.4
Jan. 2004
R0201-BS62LV2000
4
BSI
BS62LV2000
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
t
t
ACS1
ACS2
CE2
(5)
CHZ2
t
CHZ1,
t
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
t
OLZ
CE1
(5)
t
ACS1
t
t
OHZ
(1,5)
(5)
t
t
CLZ1
CHZ1
CE2
t
ACS2
(2,5)
CHZ2
t
(5)
CLZ2
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL
.
±
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.4
Jan. 2004
R0201-BS62LV2000
5
BSI
BS62LV2000
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
PARAMETER
CYCLE TIME : 100ns
MIN. TYP. MAX.
DESCRIPTION
UNIT
MIN. TYP. MAX.
NAME
tAVAX
t E1LWH
tAVWL
tAVWH
tWLWH
tWHAX
t E2LAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tWC
Write Cycle Time
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tAS
Chip Select to End of Write
Address Set up Time
--
--
tAW
Address Valid to End of Write
Write Pulse Width
70
35
0
--
100
50
0
--
tWP
--
--
tWR1
tWR2
tWHZ
tDW
tDH
Write Recovery Time
(CE1 , WE)
(CE2)
--
--
Write Recovery Time
0
--
0
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
0
30
--
0
40
--
30
0
40
0
--
--
tOHZ
tOW
Output Disable to Output in High Z
End of Write to Output Active
0
30
--
0
40
--
5
10
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR1
t
(11)
CW
t
(5)
CE1
(5)
(11)
(2)
CE2
t
t
CW
WP
t
WR2
t
AW
(3)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.4
R0201-BS62LV2000
6
Jan.
2004
BSI
BS62LV2000
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE1
(11)
CW
CE2
t
t
WR2
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
t
t
OW
DH
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
±
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 2.4
R0201-BS62LV2000
7
Jan.
2004
BSI
BS62LV2000
ORDERING INFORMATION
BS62LV2000 X X Z Y Y
SPEED
70: 70ns
10: 100ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
STSOP - 32
Revision 2.4
Jan. 2004
R0201-BS62LV2000
8
BSI
BS62LV2000
PACKAGE DIMENSIONS (continued)
TSOP - 32
b
WITH PLATING
c
c1
BASE METAL
b1
SECTION A-A
SOP -32
Revision 2.4
R0201-BS62LV2000
9
Jan.
2004
相关型号:
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