BS62LV2007 [BSI]
Very Low Power/Voltage CMOS SRAM 256K X 8 bit; 非常低的功率/电压CMOS SRAM 256K ×8位
| 型号： | BS62LV2007 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| 文件： | 总9页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BS62LV2007
BSI
DESCRIPTION
FEATURES
The BS62LV2007 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
The BS62LV2007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2007 is available in the JEDEC standard 36 pin
Mini BGA 6x8 mm.
-70
-10
70ns(Max.) at Vcc = 3.0V
100ns(Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
PKG
(ICCSB1, Max)
(ICC, Max)
Vcc=
TEMPERATURE
RANGE
TYPE
Vcc=
Vcc=
Vcc=
3.0V
Vcc=
3.0V
3.0V
5.0V
5.0V
BS62LV2007HC
BS62LV2007HI
0 O C to +70 O C
70/100
70/100
6 uA
0.7 uA
1.5 uA
35 mA
20 mA
25 mA
BGA-36-
0608
2.4V ~5.5V
-40 O C to +85O C
25 uA
40 mA
BLOCK DIAGRAM
PIN CONFIGURATIONS
A13
A17
A15
Address
Memory Array
1024 x 2048
A16
20
1024
Row
A14
A12
A7
Input
Decoder
Buffer
A6
A5
A4
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Column I/O
8
Input
Buffer
Write Driver
Sense Amp
8
8
Data
256
Output
Buffer
Column Decoder
16
CE1
CE2
WE
Control
Address Input Buffer
OE
Vdd
Gnd
A9 A8 A3 A2 A1 A0 A10
A11
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.0
April 2002
R0201-BS62LV2007
1
BSI
BS62LV2007
PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0 – DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
X
CE1
H
X
CE2
X
L
OE
X
X
I/O OPERATION
High Z
Vcc CURRENT
Not selected
ICCSB, ICCSB1
(Power Down)
Output Disabled
Read
H
H
L
L
L
L
H
H
H
H
L
X
High Z
ICC
ICC
ICC
OUT
D
IN
Write
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
PARAMETER
RATING
UNITS
AMBIENT
TEMPERATURE
0 O C to +70 O
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
V
TERM
BIAS
STG
T
V
T
T
P
Vcc+0.5
Commercial
Industrial
C
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
-40 O C to +85O
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
CIN
PARAMETER
CONDITIONS
VIN=0V
MAX.
UNIT
pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
6
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
Revision 2.0
April 2002
R0201-BS62LV2007
2
BSI
BS62LV2007
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
UNITS
NAME
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Guaranteed Input Low
VIL
-0.5
--
0.8
V
Voltage(2)
2.0
2.2
--
Guaranteed Input High
Voltage(2)
VIH
IIL
--
--
Vcc+0.2
1
V
IN
Input Leakage Current
Vcc = Max, V = 0V to Vcc
uA
Vcc = Max, CE1= VIH, CE2= VIL, or
OE = VIH, VI/O = 0V to Vcc
IOL
Output Leakage Current
--
--
1
uA
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, IOL = 2mA
Vcc = Min, IOH = -1mA
--
--
--
0.4
--
V
V
2.4
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
--
--
--
--
--
--
--
--
20
35
1
IL
IH
Operating Power Supply CE1 = V , or CE2 = V ,
ICC
mA
mA
uA
Current
I
DQ = 0mA, F = Fmax(3)
--
CE1 = VIH, or CE2 = VIL
,
ICCSB
Standby Current-TTL
I
DQ = 0mA, F = Fmax(3)
--
2
0.1
0.6
0.7
6
CE1ЊVcc-0.2V, CE2Љ0.2V,
INЊVcc-0.2V or VINЉ0.2V
ICCSB1
Standby Current-CMOS
V
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
ICCDR
Data Retention Current
--
0
0.01
0.5
uA
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
VDR Њ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
CE2 Љ 0.2V
VIL
VIL
CE2
Revision 2.0
April 2002
R0201-BS62LV2007
3
BSI
BS62LV2007
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
Ω
Ω
1269
1269
CHANGE
3.3V
OUTPUT
3.3V
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
ANY CHANGE
PERMITTED
100PF
5PF
INCLUDING
INCLUDING
UNKNOWN
Ω
Ω
1404
1404
JIG AND
SCOPE
JIG AND
SCOPE
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
BS62LV2007-70
MIN. TYP. MAX.
BS62LV2007-10
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
UNIT
tAVAX
tAVQV
tE1LQV
tE2HOV
tGLQV
tE1LQX
tE2HOX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
tRC
tAA
Read Cycle Time
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACS1
tACS2
tOE
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ1
tOHZ
Chip Select Access Time
(CE1)
(CE2)
--
--
--
--
--
--
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
(CE1)
(CE2)
10
10
10
0
0
0
15
15
15
0
0
0
--
--
35
35
30
--
--
40
40
35
(CE1)
(CE2)
tAXOX
tOH
Output Disable to Output Address Change
10
--
--
15
--
--
ns
Revision 2.0
April 2002
R0201-BS62LV2007
4
BSI
BS62LV2007
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
t
t
ACS1
ACS2
CE2
(5)
(5)
CLZ
t
CHZ1, t CHZ2
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
t
OLZ
CE1
(5)
(1,5)
t
ACS1
t
tOCHHZZ1
(5)
CLZ1
t
t
CE2
t
ACS2
(2,5)
CHZ2
t
(5)
CLZ2
D OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.0
April 2002
R0201-BS62LV2007
5
BSI
BS62LV2007
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
WRITE CYCLE
JEDEC
PARAMETER
BS62LV2007-70
BS62LV2007-10
UNIT
PARAMETER
DESCRIPTION
MIN. TYP. MAX.
MIN. TYP. MAX.
NAME
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tE2LAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tWC
tCW
tAS
Write Cycle Time
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set up Time
--
--
tAW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
70
35
0
--
100
50
0
--
--
--
Write Recovery Time
(CE1 , WE)
(CE2)
--
--
Write Recovery Time
0
--
0
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
0
30
--
0
40
--
30
0
40
0
--
--
tOHZ
tOW
Output Disable to Output in High Z
End of Write to Output Active
0
30
--
0
40
--
5
10
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
t
t
WR1
(11)
CW
t
(5)
CE1
(5)
(11)
(2)
CE2
t
t
CW
WP
WR2
t
AW
(3)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
D IN
Revision 2.0
April 2002
R0201-BS62LV2007
6
BSI
BS62LV2007
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE1
(11)
CE2
t
CW
t
WR2
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 2.0
April 2002
R0201-BS62LV2007
7
BSI
BS62LV2007
ORDERING INFORMATION
BS62LV2007
X X ˀˀ Y Y
SPEED
70: 70ns
10: 100ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
H : 36 Pin Mini BGA (6mm x 8mm)
PACKAGE DIMENSIONS
A1 Ball Pad Corner
A1 Ball Pad Corner
6
5 4 3 2 1
SOLDER BALL
A
B
C
D
E
F
G
H
6.0±0.1
DETAIL A
DETAIL A
0.75
3.75
1.125
TOP VIEW
BOTTOM VIEW ( BALL SIDE )
NOTE:
1. PIN#1 DOT MARKING IS BY LASER OR PAD PRINT.
SIDE VIEW
36 mini-BGA (6 x 8)
Revision 2.0
April 2002
R0201-BS62LV2007
8
BSI
BS62LV2007
REVISION HISTORY
Revision Description
Date
Note
1.0
Data Sheet release
Jan. 10, 2002
2.0
Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 10uA to 25uA.
April,12,2002
Revision 2.0
April 2002
R0201-BS62LV2007
9
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