BS62LV2009STIG70 [BSI]
Very Low Power/Voltage CMOS SRAM 256K X 8 bit; 非常低的功率/电压CMOS SRAM 256K ×8位
| 型号： | BS62LV2009STIG70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| 文件： | 总9页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BSI
BS62LV2009
FEATURES
DESCRIPTION
• Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
The BS62LV2009 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
Vcc = 3.0V C-grade: 22mA (@55ns) operating current
I -grade: 23mA (@55ns) operating current
C-grade: 17mA (@70ns) operating current
I -grade: 18mA (@70ns) operating current
0.3uA(Typ.) CMOS standbycurrent
• High speed access time :
-55
-70
55ns
70ns
The BS62LV2009 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2009 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
55ns: 3.0~3.6V
70ns: 2.7~3.6V
Vcc=3.0V
Vcc=3.0V
55ns
70ns
BS62LV2009DC
BS62LV2009TC
BS62LV2009STC
BS62LV2009SC
BS62LV2009DI
BS62LV2009TI
BS62LV2009STI
BS62LV2016SI
DICE
TSOP-32
STSOP-32
SOP-32
DICE
TSOP-32
STSOP-32
SOP-32
+0 O C to +70O
-40 O C to +85O
C
C
2.4V ~3.6V
2.4V ~ 3.6V
55/70
55/70
22mA
23mA
3uA
17mA
5uA
18mA
BLOCK DIAGRAM
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
A17
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A15
A16
A14
Address
Memory Array
20
1024
BS62LV2009TC
BS62LV2009STC
BS62LV2009TI
BS62LV2009STI
Row
Input
A12
A7
A6
A5
A4
9
1024 x 2048
Decoder
Buffer
10
11
12
13
14
15
16
A6
A5
A4
A1
A2
A3
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
A17
A16
A14
A12
A7
1
VCC
A15
CE2
WE
32
8
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
8
Data
Output
Buffer
3
256
4
5
A13
A8
Column Decoder
16
A6
6
A5
7
A9
BS62LV2009SC
BS62LV2009SI
A4
8
A11
OE
CE1
CE2
A3
9
Control
Address Input Buffer
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
WE
OE
Vdd
Gnd
A1
A0
DQ0
DQ1
DQ2
GND
A9 A8 A3 A2 A1 A0 A10
A11
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
Jan. 2004
R0201-BS62LV2009
1
BS62LV2009
BSI
PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
CE1
H
CE2
X
OE
X
I/O OPERATION
High Z
Vcc CURRENT
Not selected
(Power Down)
I
CCSB, ICCSB1
X
X
L
X
Output Disabled
Read
H
L
H
H
L
High Z
ICC
ICC
ICC
OUT
H
L
H
D
IN
Write
L
L
H
X
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
TEMPERATURE
0 O C to +70 O
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
UNITS
RANGE
Vcc
V
Commercial
Industrial
C
2.4V ~ 3.6V
2.4V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
O C
W
-40 O C to +85O
C
PT
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
IOUT
SYMBOL
PARAMETER
CONDITIONS
IN
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
V
=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
Revision 1.1
Jan. 2004
R0201-BS62LV2009
2
BS62LV2009
BSI
DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
NAME
Guaranteed Input Low
Voltage(3)
Vcc=3.0V
Vcc=3.0V
IL
V
-0.5
--
0.8
V
Guaranteed Input High
IH
V
cc+0.3
1
2.0
--
--
--
V
V
Voltage(3)
IL
IN
I
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
uA
Vcc = Max, CE1= VIH, CE2= VIL, or
OE = VIH, VI/O = 0V to Vcc
LO
OL
I
--
--
1
uA
Vcc=3.0V
Vcc=3.0V
V
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2.0mA
OL
--
--
--
0.4
--
V
V
OH
OH
Vcc = Min, I = -1.0mA
2.4
70ns
55ns
18
23
Operating Power Supply CE1 = VIL, CE2 = VIH
Current
,
(5)
CC
3.0 V
I
I
I
--
--
--
--
--
mA
mA
uA
I
DQ = 0mA, F = Fmax(2)
CE1 = VIH, or CE2 = VIL
DQ = 0mA,
,
Vcc=3.0V
CCSB
Standby Current-TTL
0.5
5
I
CE1≧Vcc-0.2V or CE2≦0.2V,
VIN≧Vcc-0.2V or VIN≦0.2V
(4)
Vcc=3.0V
CCSB1
Standby Current-CMOS
0.3
1. Typical characteristics are at TA = 25oC.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. IccsB1 _Max. is 3uA at Vcc=3.0V and TA=70oC. 5. Icc_Max. is 22mA(@55ns) /17mA(@70ns) at Vcc=3.0V and TA=0~70oC.
2. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(3)
ICCDR
Data Retention Current
--
0
0.1
1.0
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR_MAX. is 0.7uA at TA=70oC.
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
CE1
t
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR ≧ 1.5V
V
Vcc
Vcc
Vcc
t
R
t
CDR
CE2 ≦ 0.2V
VIL
VIL
CE2
Revision 1.1
R0201-BS62LV2009
3
Jan.
2004
BS62LV2009
BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
0.5Vcc
Timing Reference Level
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 100pF+1TTL
CL = 30pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC)
READ CYCLE
JEDEC
PARAMETER
CYCLE TIME : 55ns
CYCLE TIME : 70ns
PARAMETER
(Vcc = 3.0~3.6V)
(Vcc = 2.7~3.6V)
DESCRIPTION
Read Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
NAME
t
t
55
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
30
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
AVQV
AA
t
t
Chip Select Access Time
--
--
(CE1)
(CE2)
E1LQV
ACS1
t
t
Chip Select Access Time
--
--
E2HOV
ACS2
t
t
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
GLQV
OE
t
t
10
10
5
10
10
5
(CE1)
(CE2)
E1LQX
CLZ1
t
t
--
--
E2HOX
CLZ2
t
t
--
--
GLQX
OLZ
t
t
(CE1)
(CE2)
--
30
30
25
--
35
35
30
E1HQZ
CHZ1
t
t
--
--
E2HQZ
CHZ2
t
t
--
--
GHQZ
OHZ
t
t
Data Hold from Address Change
AXOX
OH
10
--
--
10
--
--
ns
Revision 1.1
Jan. 2004
R0201-BS62LV2009
4
BS62LV2009
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
t
t
ACS1
CE2
ACS2
(5)
t
CHZ1,
t
CHZ2
(5)
t
CLZ
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
t
OLZ
CE1
(5)
t
ACS1
t
t
OHZ
(1,5)
(5)
CLZ1
t
t
CHZ1
CE2
t
ACS2
(2,5)
CHZ2
t
(5)
CLZ2
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
Revision 1.1
Jan. 2004
R0201-BS62LV2009
5
BS62LV2009
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
BS62LV2009-55
(Vcc = 3.0~3.6V)
BS62LV2009-70
PARAMETER
(Vcc = 2.7~3.6V)
DESCRIPTION
Write Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tGHQZ
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
Chip Select to End of Write
Address Setup Time
--
--
Address Valid to End of Write
Write Pulse Width
55
30
0
--
70
35
0
--
tAW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
--
--
Write recovery Time
--
--
(CE1,WE)
(CE2)
Write recovery Time
0
--
0
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
--
25
--
--
30
--
25
0
30
0
--
--
--
25
--
30
tOHZ
tWHOX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR1
t
(11)
t
CW
(5)
CE1
(5)
(11)
(2)
CE2
t
t
CW
WP
t
WR2
t
AW
(3)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 1.1
Jan. 2004
R0201-BS62LV2009
6
BS62LV2009
BSI
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE1
(11)
CW
CE2
t
t
WR2
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
(7)
(8)
t
WHZ
t
t
OW
DH
D OUT
t
DW
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 1.1
R0201-BS62LV2009
7
Jan.
2004
BS62LV2009
BSI
ORDERING INFORMATION
BS62LV2009 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
STSOP - 32
Revision 1.1
Jan. 2004
R0201-BS62LV2009
8
BS62LV2009
BSI
PACKAGE DIMENSIONS (continued)
TSOP - 32
b
WITH PLATING
c
c1
BASE METAL
b1
SECTION A-A
SOP -32
Revision 1.1
R0201-BS62LV2009
9
Jan.
2004
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