BS62LV2563JC [BSI]
Very Low Power/Voltage CMOS SRAM 32K X 8 bit; 非常低的功率/电压CMOS SRAM 32K ×8位
| 型号： | BS62LV2563JC |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 32K X 8 bit |
| 文件： | 总11页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
32K X 8 bit
BSI
BS62LV2563
DESCRIPTION
FEATURES
The BS62LV2563 is a high performance, very low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.01uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
• Wide Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS62LV2563 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2563 is available in the JEDEC standard 28 pin
330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and
8mmx13.4mm TSOP (normal type).
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
PRODUCT
FAMILY
OPERATING
Vcc
PKG
STANDBY
Operating
(ns)
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
RANGE
TYPE
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
BS62LV2563SC
BS62LV2563TC
BS62LV2563PC
BS62LV2563JC
BS62LV2563DC
BS62LV2563SI
BS62LV2563TI
BS62LV2563PI
BS62LV2563JI
BS62LV2563DI
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
0O C to +70O C
2.4V ~ 3.6V
70
70
0.2uA
20mA
-40 O C to +85 O C 2.4V ~ 3.6V
0.4uA
25mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
VCC
WE
A13
A8
A9
A11
OE
A5
A6
A7
A12
A14
A13
A8
A9
Address
BS62LV2563SC
BS62LV2563SI
BS62LV2563PC
Memory Array
512 x 512
18
512
Row
Input
BS62LV2563PI 22
BS62LV2563JC
Decoder
Buffer
21
A10
CE
BS62LV2563JI
9
20
19
18
17
16
15
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
A11
DQ0
DQ1
DQ2
GND
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Column I/O
8
Input
Buffer
Write Driver
Sense Amp
8
8
Data
64
A10
CE
Output
Buffer
1
28
OE
A11
A9
2
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
3
Column Decoder
12
4
A8
5
A13
WE
VCC
A14
A12
A7
6
CE
WE
OE
BS62LV2563TC
BS62LV2563TI
7
Control
8
Address Input Buffer
9
10
11
12
13
14
Vdd
Gnd
A6
A5
A4 A3 A2 A1 A0 A10
A1
A4
A2
A3
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.2
April 2001
R0201-BS62LV2563
1
BSI
BS62LV2563
PIN DESCRIPTIONS
Name
Function
A0-A14 Address Input
These 15 address inputs select one of the 32768 x 8-bit wordsin the RAM
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. If chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
Not selected
Output Disabled
Read
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High Z
Vcc CURRENT
ICCSB, ICCSB1
High Z
ICC
ICC
ICC
OUT
D
IN
D
Write
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
PARAMETER
RATING
UNITS
AMBIENT
TEMPERATURE
0 O C to +70 O
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
V
TERM
V
Vcc+0.5
Commercial
Industrial
C
2.4V ~ 3.6V
2.4V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
BIAS
T
T
P
-40 O C to +85O
C
STG
T
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
CIN
PARAMETER
CONDITIONS
VIN=0V
MAX.
6
UNIT
pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
Revision 2.2
April 2001
R0201-BS62LV2563
2
BSI
BS62LV2563
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN. TYP.(1) MAX.
UNITS
NAME
Guaranteed Input Low
Vcc=3.0V
Vcc=3.0V
VIL
-0.5
--
0.8
V
Voltage(2)
Guaranteed Input High
Voltage(2)
VIH
IIL
2.0
--
--
--
Vcc+0.2
1
V
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
Vcc = Max, CE = VIH, or OE = VIH
uA
,
IOL
Output Leakage Current
--
--
1
uA
V
I/O = 0V to Vcc
Vcc=3.0V
Vcc=3.0V
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, IOL = 2mA
Vcc = Min, IOH = -1mA
--
--
--
0.4
--
V
V
2.4
Operating Power Supply
Current
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
ICC
CE = VIL, IDQ = 0mA, F = Fmax(3)
--
--
--
--
--
20
1
mA
mA
uA
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
CE Њ Vcc-0.2V,
ICCSB1
Standby Current-CMOS
0.01
0.2
V
IN Њ Vcc - 0.2V or VIN Љ 0.2V
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC)
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNITS
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE Њ Vcc -0.2V
ICCDR
Data Retention Current
--
0
0.01
0.20
uA
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
t
Vcc
CE
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
Revision 2.2
April 2001
R0201-BS62LV2563
3
BS62LV2563
BSI
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times 5ns
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
Ω
Ω
1269
1269
CHANGE
3.3V
OUTPUT
3.3V
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
ANY CHANGE
PERMITTED
100PF
5PF
INCLUDING
INCLUDING
UNKNOWN
Ω
Ω
1404
1404
JIG AND
SCOPE
JIG AND
SCOPE
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC,Vcc=3.0V)
READ CYCLE
JEDEC
PARAMETER
BS62LV2563-70
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
MIN. TYP. MAX.
NAME
tAVAX
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
70
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
--
--
70
70
50
--
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
10
10
0
--
35
30
0
tAXOX
tOH
Output Disable to Output Address Change
10
--
--
ns
Revision 2.2
April 2001
R0201-BS62LV2563
4
BSI
BS62LV2563
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
(5)
t
CHZ
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
t
ACS
t
OHZ
(1,5)
t
CHZ
(5)
CLZ
t
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.2
April 2001
R0201-BS62LV2563
5
BSI
BS62LV2563
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V )
WRITE CYCLE
JEDEC
PARAMETER
BS62LV2563-70
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Write Cycle Time
UNIT
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tWC
70
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tAS
Chip Select to End of Write
Address Set up Time
70
0
--
--
tAW
tWP
tWR
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
70
50
0
--
--
Write Recovery Time
(CE , WE)
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End ot Write to Output Active
--
30
--
40
0
--
tOHZ
tOW
0
30
--
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(11)
CW
t
(5)
CE
t
AW
t
WP
(2)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
D IN
Revision 2.2
April 2001
R0201-BS62LV2563
6
BSI
BS62LV2563
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
CE
(11)
CW
t
(5)
t
AW
t
WP
(2)
t
DH
WE
t
AS
(4,10)
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 2.2
April 2001
R0201-BS62LV2563
7
BSI
BS62LV2563
ORDERING INFORMATION
BS62LV2563
X X ˀˀ Y Y
SPEED
70: 70ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 13.4mm)
D: DICE
PACKAGE DIMENSIONS
0.020 ̈́ 0.005X45̓
θ
b
WITH PLATING
c
c1
BASE METAL
b1
SOP - 28
Revision 2.2
April 2001
R0201-BS62LV2563
8
BSI
BS62LV2563
PACKAGE DIMENSIONS (continued)
UNIT
SYMBOL
INCH
MM
12̓(2x)
12̓(2x)
A
0.0433̈́0.004
1.10̈́0.10
A1 0.0045̈́0.0026 0.115̈́0.065
HD
c
L
A2 0.039̈́0.002
1.00̈́0.05
0.22̈́0.05
0.20̈́0.03
0.10 ~ 0.21
0.10 ~ 0.16
11.80̈́0.10
8.00̈́0.10
0.55̈́0.10
13.40̈́0.20
b
b1
c
c1
D
E
0.009̈́0.002
0.008̈́0.001
0.004 ~ 0.008
0.004 ~ 0.006
0.465̈́0.004
0.315̈́0.004
0.022̈́0.004
1
28
y
Seating Plane
e
14
15
̓
12 (2X)
HD 0.528̈́0.008
+0.008
0.0197
- 0.004
+0.20
L
0.50
"A"
- 0.10
D
L1
y
0
0.0315̈́0.004
0.004 Max.
0̓~ 8̓
0.80̈́0.10
0.1 Max.
0̓~ 8̓
GAUGE PLANE
A
A
0
SEATING PLANE
14
15
12 (2X)
L
L1
"A" DATAIL VIEW
b
WITH PLATING
1
28
c
c1
BASE METAL
b1
SECTION A-A
TSOP - 28
PDIP - 28
Revision 2.2
April 2001
R0201-BS62LV2563
9
BS62LV2563
BSI
PACKAGE DIMENSIONS (continued)
SOJ - 28
Revision 2.2
April 2001
R0201-BS62LV2563
10
BS62LV2563
BSI
REVISION HISTORY
Revision
Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
Revision 2.2
April 2001
R0201-BS62LV2563
11
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