BS62LV4006HIG70 [BSI]
Very Low Power CMOS SRAM 512K X 8 bit; 超低功耗CMOS SRAM 512K ×8位
| 型号： | BS62LV4006HIG70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power CMOS SRAM 512K X 8 bit |
| 文件： | 总12页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power CMOS SRAM
512K X 8 bit
BS62LV4006
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
ŸWide VCC operation voltage : 2.4V ~ 5.5V
ŸVery low power consumption :
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.25uA at 3.0V/25OC and maximum access time of 55ns at
3.0V/85OC.
VCC = 3.0V
VCC = 5.0V
Operation current : 30mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.25uA (Typ.)at 25OC
Operation current : 70mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 1.5uA (Typ.) at 25OC
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
ŸHigh speed access time :
-55
-70
55ns (Max.) at VCC=3.0~5.5V
70ns (Max.) at VCC=2.7~5.5V
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE and OE options
ŸThree state outputs and TTL compatible
ŸFully static operation
The BS62LV4006 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV4006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 600mil Plastic DIP, 400 mil TSOP II,
8mmx13.4mm STSOP and 8mmx20mm TSOP package.
ŸData retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=5V
10MHz
VCC=3V
10MHz
VCC=5.0V VCC=3.0V
1MHz
fMax.
1MHz
fMax.
BS62LV4006DC
BS62LV4006EC
BS62LV4006HC
BS62LV4006PC
BS62LV4006SC
BS62LV4006STC
BS62LV4006TC
BS62LV4006EI
BS62LV4006HI
BS62LV4006PI
BS62LV4006SI
BS62LV4006STI
BS62LV4006TI
DICE
TSOP II-32
BGA-36-0608
PDIP-32
Commercial
10uA
20uA
2.0uA
4.0uA
9mA
43mA
45mA
68mA
1.5mA
18mA
20mA
29mA
+0OC to +70OC
SOP-32
STSOP-32
TSOP-32
TSOP II-32
BGA-36-0608
PDIP-32
SOP-32
STSOP-32
TSOP-32
Industrial
10mA
70mA
2mA
30mA
-40OC to +85OC
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
A12
A14
A16
A18
A15
A17
A13
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
Address
Input
Memory Array
10
1024
BS62LV4006TC
BS62LV4006TI
BS62LV4006STC
BS62LV4006STI
Row
Decoder
1024 x 4096
9
Buffer
10
11
12
13
14
15
16
A9
A11
A6
A5
A4
A1
A2
A3
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Data
Input
Buffer
8
8
8
Column I/O
Write Driver
Sense Amp
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A18
A16
A14
A12
A7
1
8
A
B
C
D
E
F
A0
A1
NC
A3
A6
A8
Data
Output
Buffer
A15
A17
WE
A13
A8
2
256
3
DQ4
DQ5
VSS
VCC
DQ6
DQ7
A9
A2
WE
NC
A4
A5
A7
DQ0
DQ1
VCC
VSS
DQ2
DQ3
A14
4
Column Decoder
9
5
A6
6
A9
A5
7
BS62LV4006EC
BS62LV4006EI
BS62LV4006SC
BS62LV4006SI
BS62LV4006PC
BS62LV4006PI
CE
WE
A11
OE
A4
8
Control
Address Input Buffer
A3
9
OE
A10
CE
A2
10
11
12
13
14
15
16
A1
VCC
A18
CE
A17
A16
A12
DQ7
DQ6
DQ5
DQ4
DQ3
A0
A7 A6 A5 A4 A3 A2 A1 A0 A0
GND
DQ0
DQ1
DQ2
GND
G
H
OE
A15
A13
A10
A11
36-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV4006
Revision 1.4
May. 2006
1
BS62LV4006
n PIN DESCRIPTIONS
Name
Function
These 19 address inputs select one of the 524,288 x 8-bit in the RAM
A0-A18 Address Input
CE Chip Enable Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
VCC
Power Supply
Ground
GND
n TRUTH TABLE
CE
H
WE
X
OE
X
MODE
I/O OPERATION
VCC CURRENT
Not selected
(Power Down)
High Z
High Z
DOUT
ICCSB, ICCSB1
Output Disabled
Read
L
H
H
ICC
ICC
ICC
L
H
L
Write
L
L
X
DIN
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
0OC to + 70OC
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
UNITS
V
RANG
Commercial
Industrial
VCC
Terminal Voltage with
Respect to GND
-0.5(2) to 7.0
-40 to +125
-60 to +150
1.0
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under
Bias
OC
-40OC to + 85OC
TSTG
Storage Temperature
Power Dissipation
DC Output Current
OC
PT
W
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
20
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
Capacitance
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns.
Revision 1.4
May. 2006
R0201-BS62LV4006
2
BS62LV4006
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
2.4
-0.5(2)
2.2
--
TYP.(1)
MAX.
UNITS
V
NAME
VCC
--
--
--
--
--
--
--
--
--
--
5.5
VIL
VIH
IIL
Input Low Voltage
0.8
V
Input High Voltage
VCC+0.3(3)
V
VCC = Max, VIN = 0V to VCC
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
1
1
UA
UA
V
VCC = Max, CE= VIH, or OE = VIH,
VI/O = 0V to VCC
ILO
--
VOL
VOH
VCC = Max, IOL = 2.0mA
--
0.4
--
VCC = Min, IOH = -1.0mA
CE = VIL,
2.4
--
V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
30
70
2
Operating Power Supply
Current
(5)
ICC
mA
mA
mA
uA
(4)
IDQ = 0mA, f = FMAX
Operating Power Supply
Current
CE = VIL,
ICC1
--
IDQ = 0mA, f = 1MHz
10
0.5
1.0
4.0
20
CE = VIH,
IDQ = 0mA
ICCSB
Standby Current – TTL
--
0.25
1.5
VCC=3.0V
VCC=5.0V
(6)
ICCSB1
CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
Standby Current – CMOS
--
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICC (MAX.) is 29mA/68mA at VCC=3.0V/5.0V and TA=70OC.
6. ICCSB1(MAX.) is 2.0uA/10uA at VCC=3.0V/5.0V and TA=70OC.
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
TEST CONDITIONS
CE≧VCC-0.2V,
MIN.
TYP. (1)
MAX.
UNITS
VCC for Data Retention
1.5
--
--
V
VIN≧VCC-0.2V or VIN≦0.2V
(3)
CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
ICCDR
Data Retention Current
--
0
0.1
--
1.5
--
uA
ns
ns
Chip Deselect to Data
Retention Time
tCDR
tR
See Retention Waveform
(2)
Operation Recovery Time
tRC
--
--
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCRD(Max.) is 1.0uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
DR≧1.5V
VCC
VCC
VCC
tCDR
tR
CE≧VCC - 0.2V
VIH
VIH
CE
Revision 1.4
May. 2006
R0201-BS62LV4006
3
BS62LV4006
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
VCC
DON’T CARE
ANY CHANGE
PERMITTED
1 TTL
90%
90%
CHANGE :
STATE UNKNOW
Output
10%
10%
GND
(1)
®
¬
®
¬
CL
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
Rise Time :
1V/ns
Fall Time :
1V/ns
DOES NOT
APPLY
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC = 3.0~5.5V) (VCC = 2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
Read Cycle Time
55
--
--
--
--
--
--
--
--
--
--
--
55
55
30
--
70
--
--
--
--
--
--
--
--
--
--
--
70
70
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tAVQX
tE1LQV
tGLQV
tE1LQX
tGLQX
tE1HQZ
tGHQZ
tAVQX
tRC
tAA
tACS
tOE
Address Access Time
--
--
Chip Select Access Time
Output Enable to Output Valid
--
--
10
5
10
5
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Chip Select to Output Low Z
Output Enable to Output Low Z
--
--
--
30
25
--
--
35
30
--
Chip Select to Output High Z
Output Enable to Output High Z
--
--
Data Hold from Address Change
10
10
Revision 1.4
May. 2006
R0201-BS62LV4006
4
BS62LV4006
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE
tACS
(5)
tCHZ
(5)
tCLZ
DOUT
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
CE
tOH
tOE
tOLZ
tACS
(5)
tOHZ
(5)
(1,5)
tCLZ
tCHZ
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
Revision 1.4
May. 2006
R0201-BS62LV4006
5
BS62LV4006
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC = 3.0~5.5V) (VCC = 2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
Write Cycle Time
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tCW
tAS
Chip Select to End of Write
Address Set up Time
--
--
Address Valid to End of Write
Write Pulse Width
55
30
0
--
70
35
0
--
tAW
tWP
tWR
tWHZ
tDW
tDH
--
--
--
--
Write Recovery Time
Write to Output High Z
(CE, WE)
--
25
--
--
30
--
Data to Write Time Overlap
Data Hold from Write Time
25
0
30
0
--
--
Output Disable to Output in High Z
End of Write to Output Active
--
25
--
--
30
--
tOHZ
tOW
5
5
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR
(11)
tCW
(5)
CE
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision 1.4
May. 2006
R0201-BS62LV4006
6
BS62LV4006
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
CE
(11)
tCW
(5)
tAW
(2)
tWP
WE
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All
signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition
edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals
of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE going low to the end of write.
Revision 1.4
R0201-BS62LV4006
7
May.
2006
BS62LV4006
n ORDERING INFORMATION
BS62LV4006
X
X
Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
E: TSOP II
H: BGA-36-0608
P: PDIP
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
b1
BASE METAL
SECTION A-A
SOP -32
Revision 1.4
May. 2006
R0201-BS62LV4006
8
BS62LV4006
n PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
Revision 1.4
R0201-BS62LV4006
9
May.
2006
BS62LV4006
n PACKAGE DIMENSIONS (continued)
PDIP - 32
NOTES
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
36 mini-BGA (6 x 8mm)
Revision 1.4
May. 2006
R0201-BS62LV4006
10
BS62LV4006
n PACKAGE DIMENSIONS (continued)
DIMENSION
(MM)
DIMENSION
(INCH)
17
32
MIN.
NOM. MAX. MIN.
NOM. MAX.
0.047
1.20
0.15
A
A1
0.004
0.006
0.042
0.05
0.95
0.10
1.00
0.002
0.037
1.05
0.039
0.016
A2
b
0.30
0.30
0.12
0.52
0.45
0.21
0.012
0.012
0.005
0.020
0.018
0.008
b1
c
0.40
c1
D
E
0.10
0.127
20.95
0.16
0.004
0.820
0.455
0.394
0.005
0.825
0.006
0.830
0.471
0.405
21.08
11.96
10.29
20.82
11.56
10.03
11.76
0.463
1
16
e
b
"X"
E1
e
10.16
0.400
Y
Y
1.27 BASIC
0.050 BASIC
0.60
0.25
0.024
0.010
0.004
L
0.40
0.50
0.016
0.020
0.25 BASIC
0.8 REF
0.010 BASIC
0.031 REF
L1
L2
R
D
0.12
0.12
0.005
0.005
ZD
R1
0.95 REF
0.037 REF
ZD
Y
0.10
Y
SEATING PLANE
-T-
NOTE:
1. CONTROLLING DIMENSION : MILLIMETERS.
2. REFREENCE DOCUMENT : JEDEC MS-024
3. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE.
b
b1
RAD R
GAGE PLANE
4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm
L
RAD R1
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
WITH PLATING
BASE METAL
L2
DETAIL "X"
SECTION Y-Y
TSOP II - 32
Revision 1.4
May. 2006
R0201-BS62LV4006
11
BS62LV4006
n Revision History
Revision No.
1.2
History
Draft Date
Remark
To add Icc1 characteristic parameter
To improve Iccsb1 spec.
Jan. 13, 2006
I-grade from 60uA to 20uA at 5.0V
10uA to 4.0uA at 3.0V
C-grade from 30uA to 10uA at 5.0V
5.0uA to 2.0uA at 3.0V
1.3
1.4
To Add 400 mil TSOP II package type
March 20, 2006
May. 25, 2006
Change I-grade operation temperature range
- from –25OC to –40OC
Revision 1.4
R0201-BS62LV4006
12
May.
2006
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