BS62LV8001FI70 [BSI]
Very Low Power CMOS SRAM 1M X 8 bit; 超低功耗CMOS SRAM 1M ×8位
| 型号： | BS62LV8001FI70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power CMOS SRAM 1M X 8 bit |
| 文件： | 总10页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power CMOS SRAM
1M X 8 bit
BS62LV8001
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
The BS62LV8001 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
and operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.8uA at 3.0V/25OC and maximum access time of 55ns at
3.0V/85OC.
Ÿ Very low power consumption :
VCC = 3.0V
VCC = 5.0V
Operation current : 31mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.8uA (Typ.) at 25 OC
Operation current : 76mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 3.5uA (Typ.) at 25OC
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
Ÿ High speed access time :
-55
-70
55ns (Max.) at VCC : 3.0~5.5V
70ns (Max.) at VCC : 2.7~5.5V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
The BS62LV8001 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV8001 is available in DICE form, JEDEC standard 44-pin
TSOP II and 48-ball BGA package.
Ÿ Data retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=5.0V
10MHz
VCC=3.0V
10MHz
VCC=5.0V VCC=3.0V
1MHz
9mA
fMax.
1MHz
fMax.
BS62LV8001DC
BS62LV8001EC
BS62LV8001FC
BS62LV8001EI
BS62LV8001FI
DICE
Commercial
25uA
50uA
4.0uA
8.0uA
39mA
40mA
75mA
1.5mA
19mA
20mA
30mA
TSOP II-44
BGA-48-0912
TSOP II-44
BGA-48-0912
+0OC to +70OC
Industrial
10mA
76mA
2mA
31mA
-40OC to +85OC
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
VSS
DQ2
DQ3
NC
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CE2
A8
NC
A13
A17
A15
A18
A16
Address
22
2048
Memory Array
NC
Input
Row
Decoder
9
DQ7
DQ6
VSS
VCC
DQ5
DQ4
NC
A14
A12
A7
A6
A5
A4
10
11
12
13
14
15
16
17
18
19
20
21
22
Buffer
2048 x 4096
BS62LV8001EC
BS62LV8001EI
NC
NC
A9
4096
WE
A19
A18
A17
A16
A15
A10
A11
A12
A13
A14
DQ0
8
DQ1
Data
Input
Buffer
8
Column I/O
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Write Driver
Sense Amp
8
8
Data
Output
Buffer
1
2
3
4
5
6
512
A
NC
OE
A0
A1
A2
Column Decoder
CE2
18
B
C
NC
NC
NC
A3
A5
A4
A6
CE1
NC
NC
CE1
CE2
WE
OE
Control
Address Input Buffer
DQ0
VSS
VCC
DQ3
NC
DQ4
VCC
VSS
D
E
F
DQ1
DQ2
NC
A17
NC
A7
DQ5
DQ6
NC
VCC
VSS
DQ7
NC
A11 A9 A8 A3 A2 A1 A0 A10 A19
A16
A15
A13
A10
A14
A12
A9
G
H
NC
WE
A11
A18
A8
A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV8001
Revision
May.
2.3
2006
1
BS62LV8001
n PIN DESCRIPTIONS
Name
Function
These 20 address inputs select one of the 1,048,576 x 8-bit in the RAM
A0-A19 Address Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
VCC
Power Supply
Ground
VSS
n TRUTH TABLE
MODE
CE2
I/O OPERATION VCC CURRENT
CE1
WE
X
OE
X
H
X
L
L
L
X
L
Not selected
(Power Down)
High Z
ICCSB, ICCSB1
X
X
Output Disabled
Read
H
H
H
H
H
High Z
DOUT
DIN
ICC
ICC
ICC
H
L
Write
L
X
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
0OC to + 70OC
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
UNITS
V
RANG
Commercial
Industrial
VCC
Terminal Voltage with
Respect to GND
-0.5(2) to 7.0
-40 to +125
-60 to +150
1.0
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under
Bias
OC
-40OC to + 85OC
TSTG
Storage Temperature
Power Dissipation
DC Output Current
OC
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
PT
W
IOUT
20
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
Capacitance
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns.
R0201-BS62LV8001
Revision
May.
2.3
2006
2
BS62LV8001
n DC ELECTRICAL CHARACTERISTICS (TA =-40OC to +85OC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN.
2.4
-0.5(2)
2.2
--
TYP.(1)
MAX.
UNITS
NAME
VCC
Power Supply
--
--
--
--
--
--
--
--
5.5
V
V
VIL
VIH
IIL
Input Low Voltage
0.8
Input High Voltage
VCC+0.3(3)
V
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
VIN = 0V to VCC
1
1
uA
uA
V
VI/O = 0V to VCC,
CE1= VIH or CE2= VIL, or OE = VIH
ILO
--
VOL
VOH
VCC = Max, IOL = 2.0mA
--
0.4
--
VCC = Min, IOH = -1.0mA
CE1 = VIL and CE2 = VIH,
2.4
--
V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
31
76
2
Operating Power Supply
Current
(5)
ICC
mA
(4)
IDQ = 0mA, f = FMAX
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz
Operating Power Supply
Current
ICC1
--
--
--
--
--
mA
mA
uA
10
1.0
2.0
8.0
50
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
ICCSB
Standby Current – TTL
CE1≧VCC-0.2V or CE2≦0.2V,
0.8
3.5
(6)
ICCSB1
Standby Current – CMOS
V
IN≧VCC-0.2V or VIN≦0.2V
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICC (MAX.) is 30mA/75mA at VCC=3.0V/5.0V and TA=70OC.
6. ICCSB1(MAX.) is 4.0uA/25uA at VCC=3.0V/5.0V and TA=70OC.
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
VCC for Data Retention
Data Retention Current
TEST CONDITIONS
MIN.
1.5
--
TYP. (1)
MAX.
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
--
0.4
--
--
4.0
--
V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
(3)
ICCDR
uA
ns
ns
Chip Deselect to Data
Retention Time
tCDR
tR
0
See Retention Waveform
(2)
Operation Recovery Time
tRC
--
--
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCRD(Max.) is 2.0uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VDR≧1.5V
VCC
VCC
tR
VCC
tCDR
CE1≧VCC - 0.2V
VIH
VIH
CE1
R0201-BS62LV8001
Revision
May.
2.3
2006
3
BS62LV8001
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
DR≧1.5V
V
VCC
tCDR
VCC
tR
VCC
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Output Load
Others
CL = 5pF+1TTL
CL = 30pF+1TTL
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
VCC
DON’T CARE
ANY CHANGE
PERMITTED
1 TTL
90%
90%
CHANGE :
STATE UNKNOW
Output
10%
10%
GND
(1)
®
®
¬
¬
CL
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
Rise Time :
Fall Time :
1V/ns
DOES NOT
APPLY
1V/ns
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns CYCLE TIME : 70ns
PARANETER
DESCRIPTION
Read Cycle Time
(VCC = 3.0~5.5V)
(VCC = 2.7~5.5V)
UNITS
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVQX
tRC
55
--
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
25
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
30
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tE1LQV
tE2HQV
tGLQV
tE1LQX
tE2HQX
tGLQX
tE1HQZ
tE2LQZ
tGHQZ
tAVQX
tACS1
tACS2
tOE
--
--
Chip Select Access Time
Chip Select Access Time
(CE1)
(CE2)
--
--
Output Enable to Output Valid
--
--
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
10
10
10
10
--
Chip Select to Output Low Z
Chip Select to Output Low Z
(CE1)
(CE2) 10
10
--
--
Output Enable to Output Low Z
--
--
--
--
30
30
25
--
35
35
30
--
Chip Select to Output High Z
Chip Select to Output High Z
(CE1)
(CE2)
--
Output Enable to Output High Z
Data Hold from Address Change
--
--
10
10
R0201-BS62LV8001
Revision
May.
2.3
2006
4
BS62LV8001
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE1
tACS1
CE2
DOUT
tACS2
(5)
tCHZ1, tCHZ2
(5)
tCLZ
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
tOH
tOE
tOLZ
CE1
(5)
tACS1
tOH(1Z,5)
(5)
tCLZ1
tCHZ1
CE2
DOUT
tACS2
(1,5)
tCHZ2
(5)
tCLZ2
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV8001
Revision
May.
2.3
2006
5
BS62LV8001
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns CYCLE TIME : 70ns
PARANETER
DESCRIPTION
Write Cycle Time
(VCC = 3.0~5.5V)
(VCC = 2.7~5.5V)
UNITS
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVWL
tAVWH
tE1LWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS
Chip Select to End of Write
Address Set up Time
tAW
40
40
30
0
--
50
50
35
0
--
tCW
Address Valid to End of Write
Write Pulse Width
--
--
tWP
--
--
tWR1
tWR2
tWHZ
tDW
--
--
Write Recovery Time
Write Recovery Time
(CE1, WE)
(CE2)
0
--
0
--
Write to Output High Z
--
25
--
--
30
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
25
0
30
0
tDH
--
--
tOHZ
tOW
--
25
--
--
30
--
5
5
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
tCW
(5)
(5)
CE1
CE2
(11)
(2)
tCW
(3)
tWR2
tAW
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
R0201-BS62LV8001
Revision
May.
2.3
2006
6
BS62LV8001
WRITE CYCLE 2 (1,6)
ADDRESS
tWC
(11)
tCW
(5)
(5)
CE1
CE2
WE
(11)
(2)
tCW
(3)
tAW
tWR2
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62LV8001
Revision
May.
2.3
2006
7
BS62LV8001
n ORDERING INFORMATION
BS62LV8001
X
X
Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
E: TSOP II-44
F: BGA-48-0912
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
TSOP II-44
R0201-BS62LV8001
Revision
May.
2.3
2006
8
BS62LV8001
n PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
N
D
E
D1
E1
e
D1
3.375
48
12.0
9.0
5.25
3.75
0.75
SOLDER BALL 0.35 ±0.05
VIEW A
48 mini-BGA (9mm x 12mm)
R0201-BS62LV8001
Revision
May.
2.3
2006
9
BS62LV8001
n Revision History
Revision No.
2.2
History
Draft Date
Remark
Add Icc1 characteristic parameter
Improve Iccsb1 spec.
Jan. 13, 2006
I-grade from 110uA to 50uA at 5.0V
10uA to 8.0uA at 3.0V
C-grade from 55uA to 25uA at 5.0V
5.0uA to 4.0uA at 3.0V
2.3
Change I-grade operation temperature range
- from –25OC to –40OC
May. 25, 2006
Change Iccdr spec.
I-grade from 2.5uA to 4.0uA
C-grade from 1.3uA to 2.0uA
Typical from 0.8 to 0.4uA
R0201-BS62LV8001
Revision
May.
2.3
2006
10
相关型号：
©2020 ICPDF网 联系我们和版权申明