BS62UV256PCG10 [BSI]
Ultra Low Power CMOS SRAM 32K X 8 bit; 超低功耗CMOS SRAM 32K ×8位
| 型号： | BS62UV256PCG10 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power CMOS SRAM 32K X 8 bit |
| 文件： | 总10页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power CMOS SRAM
32K X 8 bit
BS62UV256
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
ŸWide VCC low operation voltage : 1.8V ~ 3.6V
n DESCRIPTION
The BS62UV256 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 32,768 by 8 bits and
operates form a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.005uA and maximum access time of 150ns in 2.0V
operation.
ŸUltra low power consumption :
VCC = 2.0V Operation current : 15mA (Max.) at 150ns
0.5mA (Max.) at 1MHz
Standby current : 0.005uA(Typ.)at 25OC
VCC = 3.0V Operation current : 25mA (Max.) at 150ns
1mA (Max.) at 1MHz
Standby current : 0.01uA (Typ.) at 25OC
ŸHigh speed access time :
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
-10
-15
100ns (Max.)
150ns (Max.)
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE and OE options
ŸThree state outputs and TTL compatible
ŸFully static operation
The BS62UV256 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62UV256 is available in DICE form, JEDEC standard 28 pin
330mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm TSOP
(normal type).
ŸData retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
1MHz
fMax.
1MHz
fMax.
BS62UV256DC
BS62UV256PC
BS62UV256SC
BS62UV256TC
BS62UV256PI
BS62UV256SI
BS62UV256TI
DICE
PDIP-28
SOP-28
TSOP-28
PDIP-28
SOP-28
TSOP-28
Commercial
0.4uA
0.7uA
0.4uA
0.9mA
1.0mA
20mA
0.6mA
0.8mA
10mA
+0OC to +70OC
Industrial
0.7uA
25mA
15mA
-40OC to +85OC
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
2
A5
A6
A7
3
A6
4
Address
Memory Array
9
512
A12
A5
5
A9
Row
A14
A13
A8
A9
A11
Input
A4
6
A11
OE
BS62UV256PC
BS62UV256PI
BS62UV256SC
BS62UV256SI
Decoder
A3
7
512X512
Buffer
A2
8
A10
CE
A1
9
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Data
Input
Buffer
8
8
8
Column I/O
Write Driver
Sense Amp
8
Data
Output
Buffer
64
OE
A11
A9
1
2
3
4
5
6
7
8
28
A10
CE
27
26
25
24
23
22
21
20
19
18
17
16
15
Column Decoder
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A8
A13
WE
VCC
A14
A12
A7
6
CE
BS62UV256TC
BS62UV256TI
Control
Address Input Buffer
WE
OE
9
10
11
12
13
14
VCC
A6
A5
A4
GND
A4 A3 A2 A1 A0 A10
A1
A2
A3
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62UV256
Revision 2.6
Sep. 2006
1
BS62UV256
n PIN DESCRIPTIONS
Name
Function
These 15 address inputs select one of the 32,768 x 8-bit in the RAM
A0-A14 Address Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
VCC
Power Supply
Ground
GND
n TRUTH TABLE
MODE
CE
H
WE
X
OE
X
I/O OPERATION
VCC CURRENT
Not selected
(Power Down)
High Z
High Z
DOUT
ICCSB, ICCSB1
Output Disabled
Read
L
H
H
ICC
ICC
ICC
L
H
L
Write
L
L
X
DIN
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
0OC to + 70OC
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
-0.5(2) to 5.0
-40 to +125
-60 to +150
1.0
UNITS
V
RANG
Commercial
Industrial
VCC
Terminal Voltage with
Respect to GND
1.8V ~ 3.6V
1.8V ~ 3.6V
Temperature Under
Bias
OC
-40OC to + 85OC
TSTG
Storage Temperature
Power Dissipation
DC Output Current
OC
PT
W
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
20
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
Capacitance
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns.
Revision 2.6
Sep. 2006
R0201-BS62UV256
2
BS62UV256
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN.
1.8
TYP.(1)
MAX.
UNITS
V
NAME
Power Supply
--
--
--
--
--
--
--
3.6
VCC
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
0.6
0.8
Input Low Voltage
-0.5(2)
V
VIL
VIH
IIL
1.4
2.2
Input High Voltage
VCC+0.3(3)
V
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
VIN = 0V to VCC
--
--
--
1
1
uA
uA
V
CE= VIH, or OE = VIH,
VI/O = 0V to VCC
ILO
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
0.2
0.4
VCC = Max, IOL = 0.1mA
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -0.1mA
VCC = Min, IOH = -1.0mA
CE = VIL,
VOL
VOH
1.6
2.4
--
--
V
--
--
15
25
Operating Power Supply
Current
(5)
ICC
mA
mA
mA
uA
(4)
--
IDQ = 0mA, f = FMAX
--
--
0.8
1.0
0.5
1.0
0.7
0.7
CE = VIL,
Operating Power Supply
Current
ICC1
--
--
IDQ = 0mA, f = 1MHz
--
--
CE = VIH,
IDQ = 0mA
Standby Current – TTL
ICCSB
--
--
--
0.005
0.01
CE≧VCC-0.2V,
(6)
ICCSB1
Standby Current – CMOS
--
VIN≧VCC-0.2V or VIN≦0.2V
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICC (MAX.) is 10mA/20mA at VCC=2.0V/3.0V and TA=70OC.
6. ICCSB1(MAX.) is 0.4uA/0.4uA at VCC=2.0V/3.0V and TA=70OC.
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
VCC for Data Retention
Data Retention Current
TEST CONDITIONS
CE≧VCC-0.2V,
MIN.
1.5
--
TYP. (1)
MAX.
UNITS
--
--
V
VIN≧VCC-0.2V or VIN≦0.2V
CE≧VCC-0.2V,
(3)
ICCDR
0.005
0.7
--
uA
ns
ns
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
Retention Time
0
--
--
tCDR
tR
See Retention Waveform
(2)
Operation Recovery Time
tRC
--
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCDR(Max.) is 0.4uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (CE Controlled)
Data Retention Mode
DR≧1.5V
V
VCC
VCC
VCC
CE
tCDR
tR
CE≧VCC - 0.2V
VIH
VIH
Revision 2.6
Sep. 2006
R0201-BS62UV256
3
BS62UV256
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
Output Load
CL
=
Others
MAY CHANGE
WILL BE CHANGE
100pF+1TTL
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
GND
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
(1)
DOES NOT
APPLY
®
¬
®
¬
CL
Rise Time :
1V/ns
Fall Time :
1V/ns
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 100ns CYCLE TIME : 150ns
MIN. TYP. MAX. MIN. TYP. MAX.
PARANETER
DESCRIPTION
UNITS
NAME
Read Cycle Time
100
--
--
--
--
--
--
--
--
--
--
--
100
100
50
--
150
--
--
--
--
--
--
--
--
--
--
--
150
150
100
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tAVQX
tE1LQV
tGLQV
tE1LQX
tGLQX
tE1HQZ
tGHQZ
tAVQX
tRC
tAA
tACS
tOE
Address Access Time
--
--
Chip Select Access Time
Output Enable to Output Valid
--
--
10
10
--
10
10
--
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Chip Select to Output Low Z
Output Enable to Output Low Z
--
--
35
30
--
35
30
--
Chip Select to Output High Z
Output Enable to Output High Z
--
--
Data Hold from Address Change
10
10
Revision 2.6
Sep. 2006
R0201-BS62UV256
4
BS62UV256
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE
tACS
(5)
tCHZ
(5)
tCLZ
DOUT
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
CE
tOH
tOE
tOLZ
tACS
(5)
tOHZ
(5)
(1,5)
tCLZ
tCHZ
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
Revision 2.6
R0201-BS62UV256
5
Sep.
2006
BS62UV256
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 100ns CYCLE TIME : 150ns
MIN. TYP. MAX. MIN. TYP. MAX.
PARANETER
DESCRIPTION
UNITS
NAME
Write Cycle Time
100
100
100
50
0
--
--
--
--
--
--
--
--
--
--
--
--
--
150
150
150
80
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tAVWH
tE1LWH
tWLWH
tAVWL
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tAW
tCW
tWP
tAS
Address Valid to End of Write
Chip Select to End of Write
Write Pulse Width
--
--
--
--
Address Set up Time
--
--
0
--
0
--
tWR
tWHZ
tDW
tDH
Write Recovery Time
(CE, WE)
Write to Output High Z
Data to Write Time Overlap
Data Hold from Write Time
--
30
--
--
30
--
40
0
40
0
--
--
Output Disable to Output in High Z
End of Write to Output Active
--
30
--
--
30
--
tOHZ
tOW
5
5
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR
(11)
tCW
(5)
CE
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision 2.6
Sep. 2006
R0201-BS62UV256
6
BS62UV256
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
CE
(11)
tCW
(5)
tAW
(2)
tWP
WE
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive. The
data input setup and hold timing should be referenced to the second transition edge of the
signal that terminates the write.
3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE going low to the end of write.
Revision 2.6
R0201-BS62UV256
7
Sep.
2006
BS62UV256
n ORDERING INFORMATION
BS62UV256
X
X
Z Y Y
SPEED
10: 100ns
15: 150ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
S: SOP
T: TSOP (8mm x 13.4mm)
P: PDIP
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
0.020 ± 0.005X45°
q
b
WITH PLATING
c
c1
b1
BASE METAL
SOP - 28
Revision 2.6
Sep. 2006
R0201-BS62UV256
8
BS62UV256
n PACKAGE DIMENSIONS (continued)
UNIT
SYMBOL
INCH
MM
1.10±0.10
0.115±0.065
1.00±0.05
0.22±0.05
0.20±0.03
0.10 ~ 0.21
0.10 ~ 0.16
11.80±0.10
8.00±0.10
0.55±0.10
13.40±0.20
12°(2x)
12°(2x)
A
0.0433±0.004
0.0045±0.0026
0.039±0.002
0.009±0.002
0.008±0.001
0.004 ~ 0.008
0.004 ~ 0.006
0.465±0.004
0.315±0.004
0.022±0.004
A1
A2
b
e
HD
c
L
1
E
28
b1
c
b
c1
D
E
y
Seating Plane
e
12°(2x)
14
15
°
HD 0.528±0.008
+0.008
+0.20
L
0.0197
- 0.004
0.50
"A"
- 0.10
D
L1
y
0.0315±0.004
0.004 Max.
0°~ 8°
0.80±0.10
0.1 Max.
0°~ 8°
GAUGE PLANE
A2
A1
A
A
A
0
0.254
0
SEATING PLANE
14
15
12°(2x)
L
L1
"A" DATAIL VIEW
b
WITH PLATING
1
28
c
c1
BASE METAL
b1
SECTION A-A
TSOP - 28
PDIP - 28
Revision 2.6
Sep. 2006
R0201-BS62UV256
9
BS62UV256
n Revision History
Revision No.
History
Draft Date
Remark
2.4
2.5
Add Icc1 characteristic parameter
Jan. 13, 2006
May. 25, 2006
Change I-grade operation temperature range
- from –25OC to –40OC
2.6
Add speed grade
-10 for 100ns
Sep. 10, 2006
Revised ICCSB1 sepc.
- from 0.2uA to 0.4uA for C-grade
- from 0.4uA to 0.7uA for I-grade
Revised ICCDR sepc.
- from 0.1uA to 0.4uA for C-grade
- from 0.2uA to 0.7uA for I-grade
Revision 2.6
R0201-BS62UV256
10
Sep.
2006
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