CLC1003IST5X [CADEKA]
Low Distortion, Low Offset, RRIO Amplifier; 低失真，低失调， RRIO放大器
| 型号： | CLC1003IST5X |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Low Distortion, Low Offset, RRIO Amplifier |
| 文件： | 总16页 (文件大小：1953K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
®
Comlinear CLC1003
Low Distortion, Low Offset, RRIO Amplifier
f e a t u r e s
General Description
nꢀ
1mV max input offset voltage
The COMLINEAR CLC1003 is a single channel, high-performance, voltage
feedback amplifier with near precision performance, low input voltage noise,
and ultra low distortion. The CLC1003 family of amplifiers offers 1mV maxi-
mum input offset voltage, 3.5nV/√Hz broadband input voltage noise, and
0.00005% THD at 1kHz. These amplifiers also provide 55MHz gain bandwidth
product and 12V/μs slew rate making them well suited for applications requir-
ing precision DC performance and high AC performance. These COMLINEAR
high-performance amplifiers also offer a rail-to-rail input and output, simplify-
ing single supply designs and offering larger dynamic range possibilities. The
inputs extend beyond the rails by 500mV.
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
0.00005% THD at 1kHz
5.3nV/√Hz input voltage noise >10kHz
-90dB/-85dB HD2/HD3 at 100kHz, RL=100Ω
<-100dB HD2 and HD3 at 10kHz, RL=1kΩ
Rail-to-Rail input and output
55MHz unity gain bandwidth
12V/μs slew rate
+80mA, -55mA output current
-40°C to +125°C operating temperature
range
nꢀ
nꢀ
nꢀ
nꢀ
Fully specified at 3V and ±5V supplies
CLC1003: Pb-free SOT23-5, SOIC-8
Future option CLC2003: Dual
The COMLINEAR CLC1003 family of amplifiers are designed to operate from
2.5V to 12V supplies and operate over the extended temperature range of
-40°C to +125°.
Future option CLC4003: Quad
a p p l i c a t i o n s
Typical Application - Current Sensing in 3-Phase Motor
nꢀ
Active filters
nꢀ
Sensor interface
nꢀ
High-speed transducer amp
VCC
nꢀ
Medical instrumentation
nꢀ
Probe equipment
nꢀ
+
Test equipment
nꢀ
lph_1
lph_2
lph_3
CLC1003
Smoke detecters
nꢀ
Hand-held analytic instruments
–
SPM
(Smart
Power
M
Module)
Ordering Information
Part Number
Package
Pb-Free
Yes
RoHS Compliant
Operating Temperature Range Packaging Method
CLC1003IST5X
CLC1003ISO8X*
CLC1003ISO8*
CLC1003AST5X
CLC1003ASO8X*
SOT23-5
SOIC-8
SOIC-8
SOT23-5
SOIC-8
SOIC-8
Yes
Yes
Yes
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
Reel
Reel
Rail
Yes
Yes
Yes
Reel
Reel
Rail
Yes
CLC1003ASO8*
Yes
*Preliminary Product Information
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
CLC1003 SOT23-5 Pin Assignments
CLC1003 SOT Pin Configuration
Pin No.
Pin Name
OUT
Description
1
2
3
4
5
Output
OUT
1
2
3
5
4
+V
S
-V
Negative supply
Positive input
Negative input
Positive supply
S
-V
S
+
-
+IN
-IN
-IN
+IN
+V
S
CLC1003 SOIC Pin Assignments
CLC1003 SOIC Pin Configuration
Pin No.
Pin Name
NC
Description
No connect
Negative input
Positive input
Negative supply
No connect
Output
1
2
3
4
5
6
7
1
2
3
4
8
7
NC
+V
NC
-IN1
-IN1
+IN1
S
-V
S
6
5
OUT
NC
+IN1
NC
-V
S
OUT
+V
Positive supply
No connect
S
NC
8
CLC2003 Pin Configuration
CLC2003 (Future Option) Pin Configuration
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
3
4
5
6
7
8
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Negative supply
1
2
3
4
8
7
+V
S
OUT1
-IN1
+IN1
OUT2
-IN2
-V
S
6
5
+IN1
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Positive supply
+IN2
-V
S
OUT2
+V
S
CLC4003 Pin Configuration
CLC4003 (Future Option) Pin Configuration
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
Output, channel 1
1
2
3
4
14
13
12
11
10
9
OUT1
-IN1
OUT4
-IN4
Negative input, channel 1
Positive input, channel 1
Positive supply
3
+IN1
4
+V
S
+IN1
+VS
+IN4
-VS
5
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
6
5
6
7
+IN2
+IN3
-IN3
7
OUT2
OUT3
-IN3
8
Output, channel 3
-IN2
9
Negative input, channel 3
Positive input, channel 3
Negative supply
8
OUT2
OUT3
10
11
12
13
14
+IN3
-V
S
+IN4
-IN4
Positive input, channel 4
Negative input, channel 4
Output, channel 4
OUT4
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
0
Max
14
Unit
Supply Voltage
V
V
Input Voltage Range
-V -0.5V
s
+V +0.5V
s
Reliability Information
Parameter
Min
-65
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
5-Lead SOT23
150
150
260
°C
°C
°C
221
100
88
°C/W
°C/W
°C/W
8-Lead SOIC
14-Lead SOIC
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range (CLC1003I)
Operating Temperature Range (CLC1003A)
Supply Voltage Range
-40
-40
2.5
+85
+125
12
°C
°C
V
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics at +3V
T = 25°C, V = +3V, R = 1kΩ, R = 1kΩ to V /2, G = 2; unless otherwise noted.
A
s
f
L
S
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Frequency Domain Response
GBWP
UGBW
BWSS
BWLS
-3dB Gain Bandwidth Product
Unity Gain Bandwidth
-3dB Bandwidth
G = 10, VOUT = 0.05Vpp
VOUT = 0.05Vpp , Rf = 0
VOUT = 0.05Vpp
31
50
MHz
MHz
MHz
MHz
24
Large Signal Bandwidth
VOUT = 2Vpp
3.3
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 2V step; (10% to 90%)
VOUT = 2V step
150
78
ns
ns
Settling Time to 0.1%
Overshoot
tS
OS
SR
VOUT = 2V step
0.3
11
%
Slew Rate
2V step
V/µs
Distortion/Noise Response
2Vpp, 10kHz, RL = 1kΩ
2Vpp, 100kHz, RL = 100Ω
2Vpp, 10kHz, RL = 1kΩ
2Vpp, 100kHz, RL = 100Ω
1Vpp, 1kHz, G=1, RL = 2kΩ
> 10kHz
-98
-85
dBc
dBc
HD2
2nd Harmonic Distortion
-95
dBc
HD3
THD
3rd Harmonic Distortion
Total Harmonic Distortion
-81
dBc
0.0005
5.5
%
nV/√Hz
nV/√Hz
en
Input Voltage Noise
> 100kHz
3.9
DC Performance
VIO
dVIO
Ib
Input Offset Voltage
Average Drift
0.088
1.3
mV
µV/°C
μA
Input Bias Current
Average Drift
-0.340
0.8
dIb
Ios
nA/°C
nA
Input Offset Current
Power Supply Rejection Ratio
Open-Loop Gain
0.2
PSRR
AOL
IS
DC
100
dB
VOUT = VS / 2
per channel
104
dB
Supply Current
1.85
mA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting, G = 1
DC , Vcm=0.5V to 2.5V
30
MΩ
Input Capacitance
1.1
pF
-0.5 to
3.5
CMIR
Common Mode Input Range
Common Mode Rejection Ratio
V
CMRR
94
dB
Output Characteristics
0.085 to
2.80
RL = 150Ω
RL = 1kΩ
V
V
VOUT
Output Voltage Swing
0.04 to
2.91
IOUT
ISC
Output Current
+75, -40
+95, -50
mA
mA
Short-Circuit Output Current
VOUT = VS / 2
nꢀꢅꢄꢈ:
1. 100% tested at 25°C
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics at ±5V
T = 25°C, V = ±5V, R = 1kΩ, R = 1kΩ to GND, G = 2; unless otherwise noted.
A
s
f
L
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Frequency Domain Response
GBWP
UGBW
BWSS
BWLS
-3dB Gain Bandwidth Product
Unity Gain Bandwidth
-3dB Bandwidth
G = 10, VOUT = 0.05Vpp
VOUT = 0.05Vpp , Rf = 0
VOUT = 0.05Vpp
35
55
MHz
MHz
MHz
MHz
25
Large Signal Bandwidth
VOUT = 2Vpp
3.6
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 2V step; (10% to 90%)
VOUT = 2V step
125
80
ns
ns
Settling Time to 0.1%
Overshoot
tS
OS
SR
VOUT = 2V step
0.3
12
%
Slew Rate
4V step
V/µs
Distortion/Noise Response
2Vpp, 10kHz, RL = 1kΩ
2Vpp, 100kHz, RL = 100Ω
2Vpp, 10kHz, RL = 1kΩ
2Vpp, 100kHz, RL = 100Ω
1Vpp, 1kHz, G=1, RL = 2kΩ
> 10kHz
-125
-90
dBc
dBc
HD2
2nd Harmonic Distortion
-127
-85
dBc
HD3
THD
3rd Harmonic Distortion
Total Harmonic Distortion
dBc
0.00005
5.3
%
nV/√Hz
nV/√Hz
en
Input Voltage Noise
> 100kHz
3.5
DC Performance
VIO
dVIO
Ib
Input Offset Voltage(1)
-1
0.050
1.3
1
mV
µV/°C
μA
Average Drift
Input Bias Current (1)
Average Drift
-2.6
-0.30
0.85
0.2
2.6
0.7
dIb
Ios
nA/°C
μA
Input Offset Current (1)
Power Supply Rejection Ratio (1)
Open-Loop Gain (1)
Supply Current (1)
PSRR
AOL
IS
DC
82
95
100
115
2.2
dB
VOUT = VS / 2
per channel
dB
2.75
mA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting, G = 1
DC , Vcm= -3V to 3V
30
1
MΩ
Input Capacitance
pF
CMIR
Common Mode Input Range
Common Mode Rejection Ratio (1)
±5.5
V
CMRR
70
95
dB
Output Characteristics
-4.826
to 4.534
RL = 150Ω
V
V
VOUT
Output Voltage Swing
RL = 1kΩ (1)
-4.7
-4.93 to
4.85
4.7
IOUT
ISC
Output Current
+80, -55
+115, -90
mA
mA
Short-Circuit Output Current
VOUT = VS / 2
nꢀꢅꢄꢈ:
1. 100% tested at 25°C
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = 1kΩ, R = 1kΩ to GND, G = 2; unless otherwise noted.
A
s
f
L
Non-Inverting Frequency Response
Inverting Frequency Response
3
1
0
G = 1
Rf = 0
0
-1
G = -1
-2
-3
-4
-5
-6
-7
G = -2
G = 2
G = -5
-3
G = 5
G = -10
G = 10
-6
VOUT = 0.05Vpp
VOUT = 0.05Vpp
-9
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. C without R
L
L
S
1
0
4
2
-1
-2
-3
-4
-5
-6
-7
CL = 500pF
s = 10Ω
R
CL = 500pF
0
CL = 1000pF
R
s = 7.5Ω
CL = 300pF
-2
CL = 3000pF
CL = 100pF
R
s = 4Ω
-4
CL = 50pF
-6
-8
CL = 10pF
VOUT = 0.05Vpp
R s = 0 Ω
VOUT = 0.05Vpp
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. V
Frequency Response vs. R
OUT
L
3
2
1
RL = 50Ω
RL = 150Ω
0
0
RL = 2.5KΩ
VOUT = 1Vpp
-1
-2
-3
-4
RL = 1KΩ
VOUT = 2Vpp
VOUT = 4Vpp
-3
-6
-5
-6
VOUT = 0.05Vpp
-9
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = 1kΩ, R = 1kΩ to GND, G = 2; unless otherwise noted.
A
s
f
L
Non-Inverting Frequency Response at V = 3V
Inverting Frequency Response at V = 3V
S
S
3
1
0
G = 1
Rf = 0
0
-1
G = -1
-2
-3
-4
-5
-6
-7
G = -2
G = 2
G = -5
-3
G = 5
G = -10
G = 10
-6
VOUT = 0.05Vpp
VOUT = 0.05Vpp
-9
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. V
at V = 3V
Frequency Response vs. R at V = 3V
OUT
S
L
S
3
2
1
RL = 50Ω
RL = 150Ω
0
0
RL = 2.5KΩ
VOUT = 1Vpp
-1
-2
-3
-4
-5
-6
RL = 1KΩ
VOUT = 2Vpp
VOUT = 2.5Vpp
-3
-6
VOUT = 0.05Vpp
-9
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
-3dB Bandwidth vs. Output Voltage at V = 3V
-3dB Bandwidth vs. Output Voltage
S
24
21
18
15
12
9
24
21
18
15
12
9
6
6
3
3
0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOUT (VPP)
VOUT (VPP)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 1kΩ, R = 1kΩ to GND, G = 2; unless otherwise noted.
A
s
f
L
Open Loop Gain and Phase vs. Frequency
CMIR
80
60
40
0
0.5
0.4
0.3
0.2
0.1
0
-75
PHASE
-150
-225
-300
-375
-450
-525
20
GAIN
0
-20
-40
-60
-0.1
10
100
1,000
10,000
100,000
1,000,000
-6
-4
-2
0
2
4
6
F R E Q ( K H z )
Vni(V)
Input Voltage Noise
CMIR at V = 3V
S
14
13
12
11
10
9
0.5
0.4
0.3
0.2
0.1
0
8
7
6
5
4
3
2
-0.1
0.0001
0.001
0.01
0.1
1
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (MHz)
Vni(V)
CMRR vs. Frequency
PSRR vs. Frequency
110
100
90
110
100
90
80
80
70
70
60
60
50
50
40
40
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
1000
1000
Frequency (MHz)
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 1kΩ, R = 1kΩ to GND, G = 2; unless otherwise noted.
A
s
f
L
2nd Harmonic Distortion vs. R
3rd Harmonic Distortion vs. R
L
L
-50
-50
-60
-60
RL = 100Ω
RL = 10KΩ
-70
-70
-80
-90
RL = 100Ω
-80
-90
RL = 10KΩ
RL = 1KΩ
RL = 1KΩ
RL = 500Ω
RL = 500Ω
-100
-100
-110
VOUT = 2Vpp
VOUT = 2Vpp
-110
100
200
300
400
500
600
700
800
900
1000
100
200
300
400
500
600
700
800
900
1000
Frequency (KHz)
Frequency (KHz)
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
OUT
OUT
-40
-30
-40
-50
-50
-60
RF=RL=1K
-60
RF=RL=1K
-70
-70
-80
-80
RF=RL=10K
RF=RL=10K
-90
-90
FREQ = 500KHz
FREQ = 500KHz
-100
-100
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7 .5
8.5
9.5
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7 .5
8.5
9.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp)
THD vs. Frequency
-65
-70
-75
-80
-85
-90
-95
-100
VOUT = 1Vpp
RL = 1K
AV+1
100
200
300
400
500
600
700
800
900
1000
Frequency (kHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 1kΩ, R = 1kΩ to GND, G = 2; unless otherwise noted.
A
s
f
L
2nd Harmonic Distortion vs. R at V = 3V
3rd Harmonic Distortion vs. R at V = 3V
L
S
L
S
-40
-40
-50
-50
RL = 100Ω
-60
-60
RL = 100Ω
-70
-70
RL = 10KΩ
RL = 1KΩ
RL = 500Ω
-80
-80
RL = 10KΩ
RL = 1KΩ
RL = 500Ω
-90
-90
VOUT = 2Vpp
VOUT = 2Vpp
-100
-100
100
200
300
400
500
600
700
800
900
1000
100
200
300
400
500
600
700
800
900
1000
Frequency (KHz)
Frequency (KHz)
2nd Harmonic Distortion vs. V
at V = 3V
3rd Harmonic Distortion vs. V
at V = 3V
OUT
S
OUT
S
-40
-50
-60
-40
-50
-60
RF=RL=10K
RF=RL=1K
RF=RL=10K
-70
-80
-70
-80
RF=RL=1K
-90
-90
FREQ = 500KHz
FREQ = 500KHz
-100
-100
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp)
Output Amplitude (Vpp)
THD vs. Frequency at V = 3V
S
-65
-70
-75
-80
-85
-90
-95
-100
VOUT = 1Vpp
RL = 1K
AV+1
100
200
300
400
500
600
700
800
900
1000
Frequency (kHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 1kΩ, R = 1kΩ to GND, G = 2; unless otherwise noted.
A
s
f
L
Small Signal Pulse Response
Small Signal Pulse Response at V = 3V
S
0.75
1.65
0.5
0.25
0
1.6
1.55
1.5
-0.25
-0.5
-0.75
1.45
1.4
1.35
0
0.5
1
1.5
2
0
0.5
1
1.5
2
T im e ( n s )
T im e ( n s )
Large Signal Pulse Response
Large Signal Pulse Response at V = 3V
S
6
3
2.5
2
4
2
0
1.5
1
-2
-4
-6
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
T im e ( n s )
T im e ( n s )
Input Offset Voltage vs. Temperature
Input Offset Voltage Distribution
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
perature, the package thermal resistance value Theta
Application Information
JA
(Ө ) is used along with the total die power dissipation.
JA
Basic Operation
T
= T
+ (Ө × P )
Junction
Ambient JA D
Figures 1 and 2 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Where T
is the temperature of the working environment.
Ambient
In order to determine P , the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
D
+Vs
6.8μF
P = P
- P
load
D
supply
Supply power is calculated by the standard power equa-
tion.
0.1μF
Input
+
-
Output
P
= V
× I
supply
supply RMS supply
RL
V
= V - V
S+ S-
supply
0.1μF
6.8μF
Rf
Power delivered to a purely resistive load is:
Rg
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
G = 1 + (Rf/Rg)
-Vs
The effective load resistor (Rload ) will need to include
eff
the effect of the feedback network. For instance,
Figure 1. Typical Non-Inverting Gain Circuit
Rload in figure 3 would be calculated as:
eff
+Vs
6.8μF
R || (R + R )
L
f
g
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
R1
0.1μF
+
Output
Rg
Input
-
RL
Here, P can be found from
0.1μF
D
Rf
P = P
+ P
- P
D
Quiescent
Dynamic Load
6.8μF
G = - (Rf/Rg)
-Vs
Quiescent power can be derived from the specified I val-
ues along with known supply voltage, V
S
For optimum input offset
voltage set R1 = Rf || Rg
. Load power
Supply
can be calculated as above with the desired signal ampli-
tudes using:
Figure 2. Typical Inverting Gain Circuit
(V
)
= V
/ √2
LOAD RMS
PEAK
Power Dissipation
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
Power dissipation should not be a factor when operating
under the stated 300 ohm load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
Assuming the load is referenced in the middle of the pow-
er rails or V /2.
supply
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the pack-
ages available.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
For a given load capacitance, adjust R to optimize the
tradeoff between settling time and bandwidth. In general,
2.5
2
S
reducing R will increase bandwidth at the expense of ad-
S
SOIC-8
ditional overshoot and ringing.
1.5
1
SOT23-6
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx003 will typically recover in less
than 20ns from an overdrive condition. Figure 5 shows the
CLC1003 in an overdriven condition.
0.5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 3. Maximum Power Derating
3
2
Driving Capacitive Loads
VIN = .8Vpp
G = 5
2
2
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
1
1
Input
1
0
0
R , between the amplifier and the load to help improve
S
Output
stability and settling performance. Refer to Figure 4.
-1
-1
-2
-2
-1
-2
-3
Input
+
-
Rs
Output
CL
RL
Rf
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
T im e ( u s )
Rg
Figure 5. Overdrive Recovery
Figure 4. Addition of R for Driving
S
Capacitive Loads
Considerations for Offset and Noise Performance
Offset Analysis
The CLC1003 family of amplifiers is capable of driving up to
300pF directly, with no series resistance. Directly driving
500pF causes over 4dB of frequency peaking, as shown in
the plot on page 6. Table 1 provides the recommended R
for various capacitive loads. The recommended R values
There are three sources of offset contribution to consider;
input bias current, input bias current mismatch, and input
offset voltage. The input bias currents are assumed to
be equal with and additional offset current in one of the
inputs to account for mismatch. The bias currents will not
S
S
result in <=1dB peaking in the frequency response. The
affect the offset as long as the parallel combination of R
f
Frequency Response vs. C plots, on page 6, illustrates
L
and R matches R . Refer to Figure 6.
g
t
the response of the CLCx003.
+V
s
R
g
R
f
C (pF)
L
R (Ω)
S
-3dB BW (MHz)
500
1000
3000
10
7.5
4
27
20
15
–
R
CLC1003
+
t
IN
R
L
-V
s
Table 1: Recommended R vs. C
S
L
Figure 6: Circuit for Evaluating Offset
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
13
Data Sheet
The first place to start is to determine the source resis- Where V
is the noise due to the external resistors and
orext
tance. If it is very small an additional resistance may need is given by:
to be added to keep the values of R and R to practical
f
g
2
2
2
F
2
RF
RF
levels. For this analysis we assume that R is the total re-
= e 1 +
+ e ∗
+ e
v
t
n
G
o
RG
RG
sistance present on the non-inverting input. This gives us
one equation that we must solve:
R = Rg||Rf
t
The complete equation can be simplified to:
This equation can be rearranged to solve for R :
g
2
2
)
2
v
= 3 ∗ 4kT ∗ G ∗RT + e G + 2 ∗ i ∗RT
(
)
(
)
(
R = (R * R ) / (R - R )
g
t
f
f
t
n n
o
The other consideration is desired gain (G) which is:
G = (1 + R /R )
f
g
It’s easy to see that the effect of amplifier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
By plugging in the value for R we get
g
R = G * R
f
t
large R values at lower gains.
t
And R can be written in terms of R and G as follows:
g
t
R = (G * R ) / (G - 1)
g
t
Layout Considerations
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
2
2
VI
=
V
+ I ∗ RT
OS
IO
OS
And the output offset is:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
2
2
VO
= G ∗
V
+ I ∗ RT
OS
IO
OS
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
R
R
f
g
+ –
+ –
• Minimize all trace lengths to reduce series inductances
–
Refer to the evaluation board layouts below for more in-
formation.
R
g
CLC1003
+
+ –
+ –
+
–
R
L
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Figure 7: Complete Equivalent Noise Circuit
The complete noise equation is given by:
Evaluation Board #
CEB002
CEB003
Products
CLC1003 in SOT23-5
CLC1003 in SOIC-8
2
)
2
2
2
2
RF
RF
v
=
v
+
e
1 +
+ i ∗ RT 1 +
+ i ∗ RF
(
o
orext
n
bp
bn
RG
RG
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 8-13. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
S
directly connected to the ground plane.
Figure 10. CEB002 Bottom View
Figure 11. CEB003 Top View
Figure 12. CEB003 Bottom View
Figure 8. CEB002 Schematic
Figure 9. CEB002 Top View
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
15
Data Sheet
Mechanical Dimensions
SOT23-5 Package
SOIC-8
For additional information regarding our products, please visit CADEKA at: cadeka.com
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Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
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