CLC2050ISO8X [CADEKA]
Low Power, 3V to 36V, Single, Dual, Quad Amplifiers; 低功耗， 3V到36V的，单，双，四通道放大器
| 型号： | CLC2050ISO8X |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Low Power, 3V to 36V, Single, Dual, Quad Amplifiers |
| 文件： | 总17页 (文件大小：2310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
Comlinear® CLC1050, CLC2050, CLC4050
Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
F E A T U R E S
General Description
n
Unity gain stable
The COMLINEAR CLC1050 (single), CLC2050 (dual), and CLC4050 (quad)
n
n
n
n
n
n
n
n
100dB voltage gain
are voltage feedback amplifiers that are internally frequency compensated to
provide unity gain stability. At unity gain (G=1), these amplifiers offer 550kHz
of bandwidth. They consume only 0.5mA of supply current over the entire
power supply operating range. The CLC1050, CLC2050, and CLC4050 are
specifically designed to operate from single or dual supply voltages.
550kHz unity gain bandwidth
0.5mA supply current
20nA input bias current
2mV input offset voltage
3V to 36V single supply voltage range
±1.5V to ±18V dual supply voltage range
Input common mode voltage range
The COMLINEAR CLC1050, CLC2050, and CLC4050 offer a common mode
voltage range that includes ground and a wide output voltage swing. The
combination of low-power, high supply voltage range, and low supply current
make these amplifiers well suited for many general purpose applications and
as alternatives to several industry standard amplifiers on the market today.
includes ground
n
0V to VS-1.5V output voltage swing
n
CLC2050: improved replacement for
industry standard LM358
n
CLC4050: Improved replacement for
industry standard LM324
Typical Application - Voltage Controlled Oscillator (VCO)
n
CLC1050: Pb-free SOT23-5
n
CLC2050: Pb-free SOIC-8
n
CLC4050: Pb-free SOIC-14
0.05µF
A P P L I C A T I O N S
R
n
Battery Charger
–
100k
51k
1/2
V
n
–
1/2
CLCx050
CC
Active Filters
CLCx050
+
Output 1
Output 2
n
Transducer amplifiers
51k
V+/2
10k
+
R/2
50k
n
General purpose controllers
51k
n
General purpose instruments
100k
Ordering Information
Part Number
Package
SOT23-5
SOIC-8
Pb-Free
Yes
RoHS Compliant
Operating Temperature Range Packaging Method
CLC1050IST5X
CLC2050ISO8X
CLC4050ISO14X
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Reel
Reel
Reel
Yes
SOIC-14
Yes
Moisture sensitivity level for all parts is MSL-1.
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
CLC1050 Pin Assignments
CLC1050 Pin Configuration
Pin No.
Pin Name
OUT
Description
1
2
3
4
5
Output
-V
Negative supply
Positive input
Negative input
Positive supply
S
OUT
-V
1
2
3
5
4
+V
S
+IN
-IN
-
+
S
-IN
+IN
+V
S
CLC2050 Pin Configuration
CLC2050 Pin Configuration
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
3
4
5
6
7
8
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Negative supply
1
2
3
4
8
7
+V
S
OUT1
-IN1
+IN1
OUT2
-IN2
-V
S
6
5
+IN1
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Positive supply
+IN2
-V
S
OUT2
+V
S
CLC4050 Pin Configuration
CLC4050 Pin Configuration
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Positive supply
1
2
3
4
14
13
12
11
10
9
3
+IN1
OUT1
-IN1
OUT4
-IN4
4
+V
S
5
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
+IN1
+VS
+IN4
-VS
6
7
OUT2
OUT3
-IN3
8
Output, channel 3
5
6
7
+IN2
+IN3
-IN3
9
Negative input, channel 3
Positive input, channel 3
Negative supply
-IN2
10
11
12
13
14
+IN3
8
OUT2
-V
S
OUT3
+IN4
-IN4
Positive input, channel 4
Negative input, channel 4
Output, channel 4
OUT4
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
0
Max
Unit
Supply Voltage
40
40
V
V
Differential Input Voltage
Input Voltage
-0.3
40
V
Power Dissipation (T = 25°C) - SOIC-8
550
800
mW
mW
A
Power Dissipation (T = 25°C) - SOIC-14
A
Reliability Information
Parameter
Min
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
SOT23-5
150
150
260
°C
°C
°C
-65
221
100
88
°C/W
°C/W
°C/W
SOIC-8
SOIC-14
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range
Supply Voltage Range
-40
+85
°C
V
3 (±1.5)
36 (±18)
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
T = 25°C (if bold, T = -40 to +85°C), V = +5V, -V = GND, R = R =2kΩ, R = 2kΩ to V /2, G = 2; unless otherwise
A
A
s
s
f
g
L
S
noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
G = +1, VOUT = 0.2Vpp, VS = 5V
G = +1, VOUT = 0.2Vpp, VS = 30V
G = +2, VOUT = 0.2Vpp, VS = 5V
G = +1, VOUT = 0.2Vpp, VS = 30V
G = +2, VOUT = 1Vpp, VS = 5V
G = +2, VOUT = 2Vpp, VS = 30V
330
550
300
422
107
76
kHz
kHz
kHz
kHz
kHz
kHz
UGBWSS
BWSS
Unity Gain Bandwidth
-3dB Bandwidth
BWLS
Large Signal Bandwidth
Time Domain Response
VOUT = 1V step; (10% to 90%), VS = 5V
VOUT = 2V step; (10% to 90%), VS = 30V
VOUT = 0.2V step
4
µs
µs
tR, tF
OS
Rise and Fall Time
5.6
1
Overshoot
Slew Rate
%
1V step, VS = 5V
200
285
V/ms
V/ms
SR
4V step, VS = 30V
Distortion/Noise Response
VOUT = 2Vpp, f = 1kHz, G = 20dB,
CL = 100pF, VS = 30V
THD
en
Total Harmonic Distortion
0.015
%
> 10kHz, VS = 5V
45
40
nV/√Hz
nV/√Hz
dB
Input Voltage Noise
Crosstalk
> 10kHz, VS = 30V
Channel-to-channel, 1kHz to 20kHz
XTALK
120
DC Performance
2
5
mV
mV
µV/°C
nA
VIO
Input Offset Voltage (1)
Average Drift
VOUT = 1.4V, RS = 0Ω, VS = 5V to 30V
7
dVIO
7
20
100
200
30
Ib
Input Bias Current (1)
VCM = 0V
nA
5
nA
IOS
Input Offset Current (1)
VCM = 0V
100
nA
70
60
85
100
100
dB
PSRR
AOL
Power Supply Rejection Ratio (1)
Open-Loop Gain (1)
DC, VS = 5V to 30V
dB
dB
+VS = 15V, RL = ≥2kΩ, VOUT = 1V to 11V
80
dB
RL = ∞, VS = 30V
RL = ∞, VS = 5V
RL = ∞, VS = 30V
RL = ∞, VS = 5V
RL = ∞, VS = 30V
RL = ∞, VS = 5V
0.65
0.45
0.7
1.5
1.0
2.0
1.2
3.0
1.2
mA
mA
mA
mA
mA
mA
Supply Current, CLC1050 (1)
Supply Current, CLC2050 (1)
Supply Current, CLC4050 (1)
IS
0.5
1.0
0.7
Input Characteristics
+VS
- 1.5
CMIR
Common Mode Input Range (1,3)
Common Mode Rejection Ratio (1)
+VS = 30V
0
V
60
70
28
dB
dB
CMRR
DC, VCM = 0V to (+VS - 1.5V)
60
Output Characteristics
26
26
27
V
V
V
V
+VS = 30V, RL = 2kΩ
+VS = 30V, RL = 10kΩ
VOH
Output Voltage Swing, High (1)
27
©2007-2009 CADEKA Microcircuits LLC
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4
Data Sheet
Electrical Characteristics continued
T = 25°C (if bold, T = -40 to +85°C), V = +5V, -V = GND, R = R =2kΩ, R = 2kΩ to V /2, G = 2; unless otherwise
A
A
s
s
f
g
L
S
noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5
20
mV
mV
mA
VOL
Output Voltage Swing, Low (1)
+VS = 5V, RL = 10kΩ
30
20
20
10
5
40
15
ISOURCE
Output Current, Sourcing (1)
VIN+ = 1V, VIN- = 0V, +VS = 15V, VOUT = 2V
VIN+ = 0V, VIN- = 1V, +VS = 15V, VOUT = 2V
mA
ISINK
Output Current, Sinking (1)
VIN+ = 0V, VIN- = 1V, +VS = 15V, VOUT = 0.2V
+VS = 15V
12
50
40
μA
ISC
Short Circuit Output Current (1)
60
mA
Notes:
1. 100% tested at 25°C. (Limits over the full temperature range are guaranteed by design.)
2. The input common mode voltage of either input signal voltage should be kept > 0.3V at 25°C. The upper end of the common-mode voltage range is +V - 1.5V at
S
25°C, but either or both inputs can go to +36V without damages, independent of the magnitude of V .
S
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics
T = 25°C, +V = 30V, -V = GND, R = R =2kΩ, R = 2kΩ, G = 2; unless otherwise noted.
A
s
s
f
g
L
Non-Inverting Frequency Response
Inverting Frequency Response
5
5
G = 1
Rf = 0
0
-5
0
-5
G = -1
G = -2
G = -5
G = 2
G = 5
-10
-15
-10
-15
G = 10
G = -10
-20
-20
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-25
-25
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. R
L
L
5
5
CL = 1nF
Rs = 0Ω
0
0
CL = 100pF
Rs = 0Ω
CL = 10nF
Rs = 0Ω
RL = 1K
RL = 2K
RL = 5K
-5
-5
-10
-15
-20
-25
CL = 5nF
Rs = 0Ω
-10
-15
-20
-25
RL = 10K
VOUT = 0.2Vpp
VOUT = 0.2Vpp
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. V
-3dB Bandwidth vs. V
OUT
OUT
5
500
0
-5
400
300
200
100
0
Vout = 2Vpp
Vout = 4Vpp
-10
-15
-20
-25
0.01
0.1
1
10
0.0
1.0
2.0
3.0
4.0
Frequency (MHz)
VOUT (VPP)
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
T = 25°C, +V = 30V, -V = GND, R = R =2kΩ, R = 2kΩ, G = 2; unless otherwise noted.
A
s
s
f
g
L
Non-Inverting Frequency Response at V = 5V
Inverting Frequency Response at V = 5V
S
S
5
5
G = 1
Rf = 0
0
-5
0
G = -1
G = -2
-5
G = 2
-10
-15
-20
-25
-10
-15
G = 5
G = -5
G = 10
G = -10
-20
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-25
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C at V = 5V
Frequency Response vs. R at V = 5V
L
S
L
S
5
5
CL = 1nF
Rs = 0Ω
0
0
CL = 100pF
Rs = 0Ω
CL = 10nF
-5
-5
RL = 1K
Rs = 0Ω
CL = 5nF
Rs = 0Ω
RL = 2K
RL = 5K
-10
-15
-20
-25
-10
-15
-20
-25
RL = 10K
VOUT = 0.2Vpp
VOUT = 0.2Vpp
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. V
at V = 5V
-3dB Bandwidth vs. V
at V = 5V
OUT
S
OUT
S
5
400
350
300
250
200
150
100
50
0
-5
Vout = 1Vpp
Vout = 2Vpp
-10
-15
-20
-25
0
0.01
0.1
1
10
0.0
0.5
1.0
1.5
2.0
Frequency (MHz)
VOUT (VPP)
©2007-2009 CADEKA Microcircuits LLC
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7
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, +V = 30V, -V = GND, R = R =2kΩ, R = 2kΩ, G = 2; unless otherwise noted.
A
s
s
f
g
L
Small Signal Pulse Response
Large Signal Pulse Response
2.65
5.00
2.60
2.55
2.50
2.45
2.40
2.35
4.00
3.00
2.00
1.00
0.00
0
10
20
30
40
50
0
10
20
30
40
50
Time (us)
Time (us)
Small Signal Pulse Response at V = 5V
Large Signal Pulse Response at V = 5V
S
S
2.65
2.60
2.55
2.50
2.45
2.40
2.35
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0
10
20
30
40
50
0
10
20
30
40
50
Time (us)
Time (us)
Supply Current vs. Supply Voltage
Input Voltage Range vs. Power Supply
1
0.9
0.8
15
CLC4050
0.7
10
0.6
NEGATIVE
POSITIVE
0.5
0.4
0.3
0.2
0.1
0
CLC2050
CLC1050
5
0
VOUT = 0.2Vpp
0
5
10
15
20
25
30
35
40
0
5
10
15
Supply Voltage (V)
Power Supply Voltage (+/-Vdc)
©2007-2009 CADEKA Microcircuits LLC
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8
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, +V = 30V, -V = GND, R = R =2kΩ, R = 2kΩ, G = 2; unless otherwise noted.
A
s
s
f
g
L
Voltage Gain vs. Supply Voltage
Input Current vs. Temperature
120
20
18
16
14
12
10
8
RL=2K
105
90
RL=20K
6
75
4
VOUT = 0.2Vpp
2
60
0
0
8
16
24
32
40
-50
-25
0
25
50
75
100
125
Power Supply Voltage (V)
Temperature(°C)
Functional Block Diagram
VCC
6µA
4µA
100µA
Q5
Q6
Q2
Q3
Cc
Q7
–
Q4
Q1
Rsc
Inputs
Output
+
Q11
Q13
Q10
Q12
50µA
Q8
Q9
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
Power Dissipation
Application Information
Power dissipation should not be a factor when operating
under the stated 2k ohm load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
Basic Operation
Figures 1, 2, and 3 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+Vs
6.8μF
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
0.1μF
Input
+
-
perature, the package thermal resistance value Theta
JA
Output
(Ө ) is used along with the total die power dissipation.
JA
RL
T
= T + (Ө × P )
Ambient JA D
Junction
0.1μF
6.8μF
Rf
Where T
is the temperature of the working environment.
Ambient
Rg
In order to determine P , the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
G = 1 + (Rf/Rg)
D
-Vs
Figure 1. Typical Non-Inverting Gain Circuit
P = P
- P
load
D
supply
+Vs
Supply power is calculated by the standard power equa-
tion.
6.8μF
R1
P
= V
× I
supply
supply RMS supply
0.1μF
+
Output
Rg
V
= V - V
S+ S-
supply
Input
-
RL
Power delivered to a purely resistive load is:
0.1μF
Rf
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
6.8μF
G = - (Rf/Rg)
-Vs
The effective load resistor (Rload ) will need to include
the effect of the feedback network. For instance,
eff
For optimum input offset
voltage set R1 = Rf ||Rg
Rload in figure 3 would be calculated as:
Figure 2. Typical Inverting Gain Circuit
eff
R || (R + R )
L
f
g
+Vs
6.8μF
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
0.1μF
Input
+
Output
Here, P can be found from
D
-
RL
P = P
+ P
- P
D
Quiescent
Dynamic Load
0.1μF
Quiescent power can be derived from the specified I val-
S
ues along with known supply voltage, V
can be calculated as above with the desired signal ampli-
tudes using:
. Load power
Supply
6.8μF
G = 1
-Vs
Figure 3. Unity Gain Circuit
©2007-2009 CADEKA Microcircuits LLC
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10
Data Sheet
(V
)
= V
/ √2
LOAD RMS
PEAK
C (pF)
L
R (Ω)
S
-3dB BW (kHz)
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
1nF
5nF
0
0
0
0
485
390
260
440
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
10nF
100
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
Assuming the load is referenced in the middle of the pow-
er rails or V /2.
supply
Table 1: Recommended R vs. C
S
L
Figure 4 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the pack-
ages available.
For a given load capacitance, adjust R to optimize the
tradeoff between settling time and bandwidth. In general,
S
reducing R will increase bandwidth at the expense of ad-
S
ditional overshoot and ringing.
2.5
SOIC-16
2
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx050 will typically recover in less
than 30ns from an overdrive condition. Figure 6 shows the
CLC1050 in an overdriven condition.
1.5
SOT23-6
1
0.5
SOT23-5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 4. Maximum Power Derating
4
3.5
3
4
VIN = 1.25Vpp
G = 5
3.5
3
Driving Capacitive Loads
Input
2.5
2
2.5
2
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance, R ,
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 5.
1.5
1
1.5
1
Output
S
0.5
0
0.5
0
-0.5
-0.5
Input
+
-
Rs
0
20
40
60
80
100
Output
Time (us)
CL
RL
Rf
Figure 6. Overdrive Recovery
Rg
Figure 5. Addition of R for Driving
S
Capacitive Loads
Table 1 provides the recommended R for various capaci-
S
tive loads. The recommended R values result in <=1dB
S
peaking in the frequency response. The Frequency Re-
sponse vs. C plot, on page 6, illustrates the response of
L
the CLCx050.
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
Figure 7. CEB002 Schematic
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
CEB006
Products
CLC1050
CLC2050
CLC4050
CEB018
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 7-14. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
directly connected to the ground plane.
S
Figure 8. CEB002 Top View
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
Figure 9. CEB002 Bottom View
Figure 11. CEB006 Top View
Figure 12. CEB006 Bottom View
Figure 10. CEB006 Schematic
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
13
Data Sheet
Figure 14 CEB018 Top View
Figure 13. CEB018 Schematic
Figure 15. CEB018 Bottom View
Typical Applications
R1
Opto Isolator
R6
VCC
–
1/2
CLCx050
AC Line
SMPS
Battery
Pack
+
GND
R7
R3
R4
R5
Current
R2
VCC
–
1/2
Sense
CLCx050
+
GND
R8
AZ431
Figure 16. Battery Charger
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
V
cc
R1
+
2V
–
+
2V
–
R3
2k
R1
2k
R2
910K
VCC
R2
–
1/2
100K
R3
–
1/2
CLCx050
CLCx050
+V
VO
+
IN
91K
I1
1mA
I2
+
RL
R4
3k
Figure 17. Power Amplifier
Figure 20. Fixed Current Sources
R1
+V1
+V2
100k
R2
R1
1M
R2
+
1/2
CLCx050
–
VO
R5
100k
100k
R3
100k
0.001µF
+V3
+V4
R6
100k
R4
–
1/2
100k
V
O
CLCx050
100k
+
R3
R5
V
cc
100k
100k
R4
100k
Figure 18. DC Summing Amplifier
Figure 21. Pulse Generator
R1
R2
100k
1M
C1
0.1µF
C1
–
1/2
CLCx050
+
0.01µF
C
O
V
O
CIN
R1
16k
R2
R
B
R
L
V
+
IN
6.2k
10k
16k
R3
1M
1/2
V
O
CLCx050
C2
R4
100k
R5
AC
V
R3
100k
CC
–
0.01µF
C2
10µF
V
O
A
= 1 + R2/R1
= 11 (As shown)
V
V
100k
A
R4
100k
fO=1kHz
Q=1
A =2
V
fO
0
Figure 19. AC-Coupled Non-Inverting Amplifier
Figure 22. DC-Coupled Low-Pass Active Filter
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
15
Data Sheet
Mechanical Dimensions
SOT23-5 Package
SOIC-8 Package
©2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
16
Data Sheet
Mechanical Dimensions continued
SOIC-14 Package
For additional information regarding our products, please visit CADEKA at: cadeka.com
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T: 970.663.5452
T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of
CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
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Copyright ©2007-2009 by CADEKA Microcircuits LLC. All rights reserved.
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