CLC2600ISO8 [CADEKA]
Dual, Triple, and Quad 300MHz Amplifiers; 双，三和四通道300MHz的放大器
| 型号： | CLC2600ISO8 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Dual, Triple, and Quad 300MHz Amplifiers |
| 文件： | 总15页 (文件大小：2092K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
®
Comlinear CLC2600, CLC3600, CLC4600
Dual, Triple, and Quad 300MHz Amplifiers
f e a t u r e s
General Description
nꢀ
0.1dB gain flatness to 95MHz
The Comlinear CLC2600 (dual), CLC3600 (triple), and CLC4600 (quad) are
high-performance, current feedback amplifiers. These amplifiers provide
300MHz unity gain bandwidth, ±0.1dB gain flatness to 95MHz, and provide
1,300V/μs slew rate exceeding the requirements of high-definition television
(HDTV)andothermultimediaapplications. TheseComlinear high-performance
amplifiers also provide ample output current to drive multiple video loads.
nꢀ
0.03%/0.04˚ differential gain/
phase error
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
230MHz -3dB bandwidth at G = 2
300MHz -3dB bandwidth at G = 1
1,300V/μs slew rate
50mA output current
3.3mA supply current
The Comlinear CLC2600, CLC3600, and CLC4600 are designed to operate
from ±5V supplies. They consume only 3.3mA of supply current per channel.
The combination of high-speed, low-power, and excellent video performance
make these amplifiers well suited for use in many general purpose, high-
speed applications including standard definition and high definition video.
Fully specified at ±5V supplies
CLC2600: Pb-free SOIC-8
CLC4600: Pb-free SOIC-14
a p p l i c a t i o n s
nꢀ
Video line drivers
nꢀ
S-Video driver
Typical Application - Driving Dual Video Loads
nꢀ
Video switchers and routers
nꢀ
ADC buffer
+Vs
nꢀ
Active filters
nꢀ
Cable drivers
nꢀ
Twisted pair driver/receiver
75Ω
Cable
75Ω
Input
Cable
75Ω
75Ω
Output A
Output B
75Ω
75Ω
75Ω
R
f
R
g
75Ω
Cable
-Vs
Ordering Information
Part Number
Package
Pb-Free
Yes
Operating Temperature Range Packaging Method
CLC2600ISO8X
CLC2600ISO8
CLC3600ISO14X
CLC3600ISO14
CLC4600ISO14X
CLC4600ISO14
SOIC-8
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Reel
Rail
Reel
Rail
Reel
Rail
SOIC-8
Yes
SOIC-14
SOIC-14
SOIC-14
SOIC-14
Yes
Yes
Yes
Yes
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
CLC2600 Pin Configuration
CLC2600 Pin Assignments
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
3
4
8
7
+V
S
OUT1
-IN1
1
2
3
4
5
6
7
8
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Negative supply
OUT2
-IN2
6
+IN1
+IN1
-V
S
5
+IN2
-V
S
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Positive supply
OUT2
+V
S
CLC3600 Pin Configuration
CLC3600 Pin Configuration
Pin No.
Pin Name
NC
Description
1
2
3
4
14
13
12
11
10
9
NC
NC
OUT2
-IN2
1
2
No Connect
NC
No Connect
3
NC
No Connect
NC
+IN2
-VS
4
+V
Positive supply
S
+VS
5
+IN1
-IN1
Positive input, channel 1
Negative input, channel 1
Output, channel 1
Output, channel 3
Negative input, channel 3
Positive input, channel 3
Negative supply
5
6
7
+IN1
+IN3
-IN3
6
7
OUT1
OUT3
-IN3
-IN1
8
8
OUT1
OUT3
9
10
11
12
13
14
+IN3
-V
S
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
OUT2
CLC4600 Pin Configuration
CLC4600 Pin Configuration
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
3
4
14
13
12
11
10
9
OUT1
-IN1
OUT4
-IN4
1
2
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Positive supply
3
+IN1
+IN1
+VS
+IN4
-VS
4
+V
S
5
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
5
6
7
+IN2
+IN3
-IN3
6
7
OUT2
OUT3
-IN3
-IN2
8
Output, channel 3
8
OUT2
OUT3
9
Negative input, channel 3
Positive input, channel 3
Negative supply
10
11
12
13
14
+IN3
-V
S
+IN4
-IN4
Positive input, channel 4
Negative input, channel 4
Output, channel 4
OUT4
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
0
Max
Unit
Supply Voltage
±7 or 14
V
V
Input Voltage Range
-V -0.5V
s
+V +0.5V
s
Reliability Information
Parameter
Min
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
8-Lead SOIC
150
150
260
°C
°C
°C
-65
100
88
°C/W
°C/W
14-Lead SOIC
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
SOIC-8
SOIC-14
2.5kV
2kV
Human Body Model (HBM)
2.5kV
Charged Device Model (CDM)
2kV
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range
-40
+85
±6
°C
V
Supply Voltage Range
±4
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
T = 25°C, V = ±5V, R = 510Ω, R = 100Ω, G = 2; unless otherwise noted.
A
s
f
L
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Frequency Domain Response
UGBW
-3dB Bandwidth
G = +1, VOUT = 0.2Vpp, Rf = 1.24kΩ
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 4Vpp
300
230
155
95
MHz
MHz
MHz
MHz
MHz
BWSS
-3dB Bandwidth
BWLS
Large Signal Bandwidth
0.1dB Gain Flatness
0.1dB Gain Flatness
BW0.1dBSS
BW0.1dBLS
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 4Vpp
55
Time Domain Response
tR, tF
tS
Rise and Fall Time
VOUT = 2V step; (10% to 90%)
VOUT = 2V step
1.8
20
ns
ns
Settling Time to 0.1%
Overshoot
OS
SR
VOUT = 0.2V step
4V step
2.5
%
Slew Rate
1300
V/µs
Distortion/Noise Response
HD2
HD3
THD
DG
2nd Harmonic Distortion
2Vpp, 1MHz
-80
-86
dBc
dBc
3rd Harmonic Distortion
Total Harmonic Distortion
Differential Gain
2Vpp, 1MHz
2Vpp, 1MHz
-79.5
0.03
0.04
6.4
dB
%
NTSC (3.58MHz), DC-coupled, RL = 150Ω
DP
Differential Phase
°
NTSC (3.58MHz), DC-coupled, RL = 150Ω
en
Input Voltage Noise
Input Current Noise (+)
Input Current Noise (-)
Crosstalk
> 1MHz
nV/√Hz
pA/√Hz
pA/√Hz
dB
in+
> 1MHz
1.0
in-
> 1MHz
9.3
Channel-to-channel 5MHz
XTALK
-56
DC Performance
VIO
Input Offset Voltage(1)
-8
-3
1.4
15
+8
3
mV
µV/°C
µA
dVIO
Ibn
Average Drift
Input Bias Current Non-inverting(1)
Average Drift
1.3
2.6
4.4
16
dIbn
Ibi
nA/°C
µA
Input Bias Current Inverting(1)
Average Drift
-18
60
18
dIbi
PSRR
AOL
nA/°C
dB
Power Supply Rejection Ratio(1)
Open-Loop Transresistance
DC
65
VOUT = VS / 2
CLC2600 Total
CLC3600 Total
CLC4600 Total
580
6.6
13.2
13.2
kΩ
10
20
20
mA
Supply Current(1)
mA
IS
mA
Input Characteristics
RIN
Input Resistance
Non-inverting
DC
19
1
MΩ
pF
V
CIN
Input Capacitance
CMIR
CMRR
Common Mode Input Range
Common Mode Rejection Ratio(1)
±2.3
57
52
dB
Output Characteristics
Closed Loop, DC
RL = 100Ω (1)
RL = 1kΩ
110
mΩ
RO
Output Resistance
-2.6
±3
2.6
V
VOUT
Output Voltage Swing
±3.3
50
V
IOUT
ISC
Output Current
mA
mA
Short-Circuit Output Current
VOUT = VS / 2
67
nꢀꢅꢄꢈ:
1. 100% tested at 25°C
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Typical Performance Characteristics
T = 25°C, V = ±5V, R = 510Ω, R = 100Ω, G = 2; unless otherwise noted.
A
s
f
L
Non-Inverting Frequency Response
Inverting Frequency Response
1
1
0
0
-1
-1
G = -10
G = 1 0
-2
-2
G = -5
G = 5
-3
-3
-4
-4
G = -2
G = 2
-5
-5
-6
-7
-6
G = 1
Rf = 1.24kΩ
VOUT = 0.2Vpp
VOUT = 0.2Vpp
G = -1
-7
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. R
L
L
1
0
2
1
RL = 5KΩ
RL = 1KΩ
CL = 1000pF
-1
-2
-3
-4
-5
-6
-7
Rs = 5 Ω
0
CL = 500pF
Rs = 9 Ω
-1
-2
-3
-4
RL = 150Ω
RL = 50Ω
CL = 100pF
Rs = 2 0 Ω
CL = 50pF
Rs = 3 0 Ω
CL = 10pF
Rs = 4 0 Ω
-5
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-6
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. V
Frequency Response vs. Temperature
OUT
1
0
1
0
-1
-2
-3
-4
-5
-6
-7
-1
-2
VOUT = 4Vpp
-3
-4
-5
-6
-7
+ 25degC
VOUT = 2Vpp
- 40degC
+ 85degC
VOUT = 1Vpp
VOUT = 2Vpp
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 510Ω, R = 100Ω, G = 2; unless otherwise noted.
A
s
f
L
Frequency Response vs. R at G=1
Frequency Response vs. R at G=2
f
f
1
3
Rf = 250Ω
Rf = 510Ω
Rf = 750Ω
0
2
1
-1
Rf = 510Ω
Rf = 1kΩ
-2
-3
-4
-5
-6
-7
0
Rf = 1kΩ
-1
-2
-3
-4
Rf = 1.24kΩ
Rf = 1.5kΩ
Rf = 1.5kΩ
G = 1
G = 2
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. R at G=5
Gain Flatness
f
1
0
0.1
0
-0.1
-0.2
-0.3
-0.4
-1
Rf = 510Ω
-2
Rf = 100Ω
-3
Rf = 200Ω
-4
-5
-6
-7
G = 5
VOUT = 2Vpp
-0.5
0.1
1
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Open Loop Transimpendance Gain/Phase vs. Frequency
Input Voltage Noise
13
12
11
10
9
1M
100k
10k
1k
0
-20
-40
-60
Phase
-80
-100
-120
-140
-160
-180
-200
8
7
6
100
10
Gain
5
4
10k
100k
1M
10M
100M
1G
0.0001 0.001 0.01
0.1
1
10
100
Frequency (Hz)
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 510Ω, R = 100Ω, G = 2; unless otherwise noted.
A
s
f
L
2nd Harmonic Distortion vs. R
3rd Harmonic Distortion vs. R
L
L
-55
-50
-55
-60
-60
RL = 100Ω
-65
RL = 100Ω
-70
-75
-80
-85
-65
-70
-75
-80
-85
-90
RL = 1kΩ
RL = 1kΩ
-90
VOUT = 2Vpp
VOUT = 2Vpp
-95
0
5
10
15
20
0
5
10
Frequency (MHz)
15
20
Frequency (MHz)
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
OUT
OUT
-55
-45
-50
-60
20MHz
20MHz
-55
-65
-60
-65
-70
-75
-70
5MHz
-75
5MHz
-80
-85
-90
-80
1MHz
-85
1MHz
-90
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
CMRR vs. Frequency
PSRR vs. Frequency
0
-20
-10
-20
-30
-40
-50
-60
-30
-40
-50
-60
-70
-80
10
100
1k
10k 100k 1M 10M 100M
10
100
1k
10k 100k 1M 10M 100M
Frequency (Hz)
Frequency (Hz)
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = 510Ω, R = 100Ω, G = 2; unless otherwise noted.
A
s
f
L
Small Signal Pulse Response
Large Signal Pulse Response
0.125
0.1
2.5
2.0
0.075
0.05
1.5
1.0
0.025
0
0.5
0.0
-0.025
-0.05
-0.075
-0.1
-0.5
-1.0
-1.5
-2.0
-2.5
-0.125
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100
120
140
160
180
200
T im e ( n s )
T im e ( n s )
Crosstalk vs. Frequency
Closed Loop Output Impedance vs. Frequency
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
0.1
10
1
VOUT = 2Vpp
0.1
1
10
100
10k
100k
1M
10M
100M
Frequency (MHz)
Frequency (Hz)
Differential Gain & Phase AC Coupled
Differential Gain & Phase DC Coupled
0.04
0.04
RL = 150Ω
DC coupled
RL = 150Ω
AC coupled into 220µF
0.03
0.02
0.01
0
0.03
0.02
0.01
0
DG
DG
-0.01
-0.02
-0.03
-0.04
-0.01
-0.02
-0.03
-0.04
DP
DP
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
-0 .7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0 .7
Input Voltage (V)
I n p u t Vo l t a g e ( V )
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
General Information - Current Feedback
Technology
Advantages of CFB Technology
V
OUT
x1
Z *I
err
o
I
err
The CLCx600 Family of amplifiers utilize current feedback
(CFB) technology to achieve superior performance. The
primary advantage of CFB technology is higher slew rate
performance when compared to voltage feedback (VFB)
architecture. High slew rate contributes directly to better
large signal pulse response, full power bandwidth, and
distortion.
R
R
g
f
R
L
V
IN
VOUT
Rf
1
=
−
+
Eq. 2
V
Rg
Rf
Zo(jω)
IN
1 +
CFB also alleviates the traditional trade-off between
closed loop gain and usable bandwidth that is seen with
a VFB amplifier. With CFB, the bandwidth is primarily de-
Figure 2. Inverting Gain Configuration with First Order
Transfer Function
termined by the value of the feedback resistor, R . By us-
f
ing optimum feedback resistor values, the bandwidth of a
CFB amplifier remains nearly constant with different gain
configurations.
CFB Technology - Theory of Operation
Figure 1 shows a simple representation of a current feed-
back amplifier that is configured in the traditional non-
inverting gain configuration.
When designing with CFB amplifiers always abide by these
basic rules:
• Use the recommended feedback resistor value
Instead of having two high-impedance inputs similar to a
VFB amplifier, the inputs of a CFB amplifier are connected
across a unity gain buffer. This buffer has a high imped-
ance input and a low impedance output. It can source or
• Do not use reactive (capacitors, diodes, inductors, etc.)
elements in the direct feedback path
• Avoid stray or parasitic capacitance across feedback re-
sistors
sink current (I ) as needed to force the non-inverting
err
input to track the value of Vin. The CFB architecture em-
ploys a high gain trans-impedance stage that senses Ierr
• Follow general high-speed amplifier layout guidelines
and drives the output to a value of (Z (jω) * I ) volts.
o
err
• Ensure proper precautions have been made for driving
capacitive loads
With the application of negative feedback, the amplifier
will drive the output to a voltage in a manner which tries
to drive Ierr to zero. In practice, primarily due to limita-
tions on the value of Z (jω), Ierr remains a small but
o
finite value.
V
IN
V
OUT
x1
Z *I
o err
I
err
A closer look at the closed loop transfer function (Eq.1)
shows the effect of the trans-impedance, Z (jω) on the
o
R
f
gain of the circuit. At low frequencies where Z (jω) is very
R
L
o
large with respect to R , the second term of the equation
f
R
g
approaches unity, allowing R and R to set the gain. At
f
g
higher frequencies, the value of Z (jω) will roll off, and
o
the effect of the secondary term will begin to dominate.
The -3dB small signal parameter specifies the frequency
VOUT
Rf
1
=
1 +
+
Eq. 1
where the value Z (jω) equals the value of R causing the
o
f
V
Rg
Rf
Zo(jω)
IN
1 +
gain to drop by 0.707 of the value at DC.
For more information regarding current feedback ampli-
fiers, visit www.cadeka.com for detailed application notes,
such as AN-3: The Ins and Outs of Current Feedback Am-
plifiers.
Figure 1. Non-Inverting Gain Configuration with First
Order Transfer Function
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
CFB amplifiers can be used in unity gain configurations.
Do not use the traditional voltage follower circuit, where
the output is tied directly to the inverting input. With a
CFB amplifier, a feedback resistor of appropriate value
must be used to prevent unstable behavior. Refer to fig-
ure 5 and Table 1. Although this seems cumbersome, it
does allow a degree of freedom to adjust the passband
characteristics.
Application Information
Basic Operation
Figures 3, 4, and 5 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+Vs
6.8μF
Feedback Resistor Selection
One of the key design considerations when using a CFB
amplifier is the selection of the feedback resistor, R . R is
f
f
0.1μF
Input
+
-
used in conjunction with R to set the gain in the tradi-
g
Output
tional non-inverting and inverting circuit configurations.
Refer to figures 3 and 4. As discussed in the Current Feed-
back Technology section, the value of the feedback resis-
tor has a pronounced effect on the frequency response of
the circuit.
RL
0.1μF
6.8μF
Rf
Rg
G = 1 + (Rf/Rg)
-Vs
Table 1, provides recommended R and associated R val-
f
g
ues for various gain settings. These values produce the
optimum frequency response, maximum bandwidth with
minimum peaking. Adjust these values to optimize perfor-
mance for a specific application. The typical performance
characteristics section includes plots that illustrate how
Figure 3. Typical Non-Inverting Gain Circuit
+Vs
6.8μF
the bandwidth is directly affected by the value of R at
various gain settings.
f
R1
0.1μF
+
Output
Rg
Input
-
RL
±0.1dB BW
(MHz)
-3dB BW
(MHz)
0.1μF
Gain
(V/V
Rf
R (Ω)
f
R (Ω)
g
6.8μF
G = - (Rf/Rg)
-Vs
1
2
5
1240
510
-
129
140
18
300
230
111
For optimum input offset
voltage set R1 = Rf || Rg
510
50
200
Figure 4. Typical Inverting Gain Circuit
Table 1: Recommended R vs. Gain
f
+Vs
In general, lowering the value of R from the recom-
6.8μF
f
mended value will extend the bandwidth at the expense
of additional high frequency gain peaking. This will cause
increased overshoot and ringing in the pulse response
0.1μF
Input
+
Output
characteristics. Reducing R too much will eventually
f
-
RL
cause oscillatory behavior.
0.1μF
Rf
Increasing the value of Rf will lower the bandwidth. Low-
ering the bandwidth creates a flatter frequency response
and improves 0.1dB bandwidth performance. This is im-
portant in applications such as video. Further increase in
Rf will cause premature gain rolloff and adversely affect
gain flatness.
6.8μF
G = 1
-Vs
Rf is required for CFB amplifiers
Figure 5. Typical Unity Gain (G=1) Circuit
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Driving Capacitive Loads
ringing. Refer to the lꢂyꢀꢊꢅ cꢀꢆꢈꢇdꢄꢃꢂꢅꢇꢀꢆꢈ section for
additional information regarding high speed layout tech-
niques.
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
Overdrive Recovery
R , between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 6.
S
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified volt-
age range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLCx600 Family will typically recover in less
than 10ns from an overdrive condition. Figure 7 shows the
CLC2600 in an overdriven condition.
Input
+
-
Rs
Output
CL
RL
Rf
Rg
Figure 6. Addition of R for Driving
S
1.00
0.75
4
Capacitive Loads
VIN = 1.5Vpp
G = 5
3
Table 2 provides the recommended R for various capaci-
S
0.50
2
tive loads. The recommended R values result in <=0.5dB
S
Input
0.25
1
peaking in the frequency response. The Frequency Re-
Output
sponse vs. C plot, on page 5, illustrates the response of
L
0.00
0
the CLCx600 Family.
-0.25
-0.50
-0.75
-1.00
-1
-2
-3
-4
C (pF)
L
R (Ω)
-3dB BW (MHz)
S
10
50
40
30
20
265
140
105
0
20
40
60
80 100 120 140 160 180 200
T im e ( n s )
100
Figure 7. Overdrive Recovery
Power Dissipation
Table 1: Recommended R vs. C
S
L
For a given load capacitance, adjust R to optimize the
tradeoff between settling time and bandwidth. In general,
S
For most applications, the power dissipation due to driv-
ing external loads should be low enough to ensure a safe
operating condition. However, applications with low im-
pedance, DC coupled loads should be analyzed to en-
sure that maximum allowed junction temperature is not
exceeded. Guidelines listed below can be used to verify
that the particular application will not cause the device to
operate beyond it’s intended operating range.
reducing R will increase bandwidth at the expense of ad-
S
ditional overshoot and ringing.
Parasitic Capacitance on the Inverting Input
Physical connections between components create unin-
tentional or parasitic resistive, capacitive, and inductive
elements.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
Parasitic capacitance at the inverting input can be espe-
cially troublesome with high frequency amplifiers. A para-
sitic capacitance on this node will be in parallel with the
perature, the package thermal resistance value Theta
JA
(Ө ) is used along with the total die power dissipation.
JA
gain setting resistor R . At high frequencies, its imped-
g
ance can begin to raise the system gain by making R
appear smaller.
g
T
= T + (Ө × P )
Ambient JA D
Junction
In general, avoid adding any additional parasitic capaci-
tance at this node. In addition, stray capacitance across
Where T
is the temperature of the working environment.
the R resistor can induce peaking and high frequency
Ambient
f
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
In order to determine P , the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
D
2.5
2
SOIC-14
P = P
- P
load
D
supply
1.5
1
Supply power is calculated by the standard power equa-
tion.
SOIC-8
P
= V
× I
supply
supply RMS supply
0.5
0
V
= V - V
S+ S-
supply
Power delivered to a purely resistive load is:
-40
-20
0
20
40
60
80
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
Ambient Temperature (°C)
The effective load resistor (Rload ) will need to include
eff
the effect of the feedback network. For instance,
Figure 8. Maximum Power Derating
Rload in figure 3 would be calculated as:
eff
R || (R + R )
Better thermal ratings can be achieved by maximizing PC
board metallization at the package pins. However, be care-
ful of stray capacitance on the input pins.
L
f
g
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load In addition, increased airflow across the package can also
impedance is needed to determine the dissipated power. help to reduce the effective Ө of the package.
JA
Here, P can be found from
D
In the event the outputs are momentarily shorted to a low
impedance path, internal circuitry and output metallization
are set to limit and handle up to 65mA of output current.
However, extended duration under these conditions may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded.
P = P
+ P
- P
D
Quiescent
Dynamic Load
Quiescent power can be derived from the specified I val-
ues along with known supply voltage, V
can be calculated as above with the desired signal ampli-
tudes using:
S
. Load power
Supply
Layout Considerations
(V
)
= V
/ √2
LOAD RMS
PEAK
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Assuming the load is referenced in the middle of the power
rails or V /2.
supply
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
Figure 8 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8 and 14 lead
SOIC packages.
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
Data Sheet
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB006
CEB018
Products
CLC2600
CLC3600, CLC4600
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 9-14. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
Figure 10. CEB006 Top View
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
S
directly connected to the ground plane.
Figure 11. CEB006 Bottom View
Figure 9. CEB006 Schematic
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
13
Data Sheet
Figure 14. CEB018 Bottom View
Figure 12. CEB018 Schematic
Figure 13. CEB018 Top View
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
Mechanical Dimensions
SOIC-8 Package
SOIC-14 Package
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Hꢄꢂdqꢊꢂꢃꢅꢄꢃꢈ Loveland, Colorado
T: 970.663.5452
T: 877.663.5415 (toll free)
CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
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Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
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