SPT1175ACU [CADEKA]
8-BIT, 20 MSPS CMOS A/D CONVERTER; 8位， 20 MSPS的CMOS A / D转换器
| 型号： | SPT1175ACU |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 8-BIT, 20 MSPS CMOS A/D CONVERTER |
| 文件： | 总8页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT1175
8-BIT, 20 MSPS CMOS A/D CONVERTER
FEATURES
APPLICATIONS
• 20 MSPS Maximum Conversion Rate
• Internal Sample-and-Hold Function
• 90 mW Power Dissipation
• Internal Voltage Reference
• Single +5.0 V Power Supply
• Three-State TTL-Outputs
• Video Digitizing
• Image Scanners
• Personal Computer Video
• Medical Ultrasound
• Multimedia
• Digital Television
• CMOS Compatible Clock
GENERAL DESCRIPTION
The SPT1175 is a CMOS two-step A/D converter capable of
digitizingfullscaleanaloginputsignalsinto8-bitdigitalwords
at a sample rate of 20 MSPS.
The SPT1175 operates from a single +5.0 V power supply
and has an internal voltage reference which eliminates the
need for external reference circuitry. All digital inputs are
CMOS compatible and the tri-state outputs are TTL-compat-
ible. The SPT1175 is ideal for most video and image pro-
cessing applications that require low power dissipation and
low cost. The SPT1175 is available in 24-lead plastic SOIC,
plastic DIP, and PLCC packages over the commercial tem-
perature range (0 to +70 °C). It is also available in die form.
For most applications, no external sample-and-hold or
video driving amplifiers are required due to the device's
narrow aperture time, wide bandwidth, and low input ca-
pacitance.
BLOCK DIAGRAM
DGND
V
V
DV
DD
RB
RBS
OE
Coarse
Sampling
Amplifier
Latch
Encoder
DØ (LSB)
D1
Data
Latches
and
3-State
Output
Buffer
D2
Error
Correction
Circuit
D3
Reference Matrix
V
IN
D4
D5
D6
Fine
Sampling
Amplifier
D7 (MSB)
Encoder
Analog
Mux
Latch
Fine
Sampling
Amplifier
Timing
Generator
CLK
AGND
AGND
V
V
AV
D
DV
DD
RT
RTS
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)(1) 25 °C
Supply Voltages
........................................................... -0.5 to +7.0 V
Input Voltages
Temperature
V
DD
Operating Temperature ................................. 0 to +70 °C
Junction Temperature ........................................... 175 °C
Lead Temperature, (soldering 10 seconds) .......... 300 °C
Storage Temperature................................ -55 to +125 °C
Analog Input.............................................. AGND to V
DD
DD
Reference Input Voltage ........................... AGND to V
(2)
ESD Susceptibility ................................................. ±1,500 V
Notes: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
2. 100 pF discharged through a 1.5 kΩ resistor (human body model).
ELECTRICAL SPECIFICATIONS
T = +25 °C, AV =DV =+5.0 V, AGND=DGND=0.0 V, V =+0.6 V and V =+2.6 V, unless otherwise specified.
A
DD
DD
RB
RT
TEST
CONDITIONS
TEST
LEVEL
SPT1175
TYP
PARAMETERS
MIN
MAX
UNITS
Resolution
8
Bits
DC Accuracy (+25 °C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
I
I
I
±0.8
±0.6
Guaranteed
±1.2
±1.0
LSB
LSB
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
I
I
VI
V
V
V
V
±5.0
V
RB
RT
µA
kΩ
pF
MHz
100
12
200
15
Reference Input
Reference Ladder Resistance
Reference Current
Reference Input Voltage
I
I
IV
IV
I
200
5.0
0
300
6.7
0.6
2.6
0.60
2.0
400
10.0
-
2.8
0.65
2.1
Ω
mA
V
V
V
V
V
V
V
RB
-
RT
RB
-V
RT RB
Internal Bias
0.55
1.9
I
V
Short V and V
RT
RTS
RBS
Short V and V
RB
Offset Voltage Error
Top
Bottom
I
I
-18
0
-25
10
-68
40
mV
mV
Timing Characteristics
Maximum Conversion Rate
Output Data Delay (td)
Output Data Delay
(Tdish, Tdisl)
1 MHz Input Sine Wave
(High Z)
I
IV
IV
20
30
18
MSPS
ns
ns
30
100
Data Valid Time
(Teneh, Tenel)
Sampling Time Offset
Tri-State Circuit
IV
IV
100
10
ns
ns
5
NOTE: It is strongly recommended that all of the supply pins (AV , DV ) be powered from the same source.
DD
DD
SPT1175
6/24/97
2
ELECTRICAL SPECIFICATIONS
T =+25 °C, AV =DV =+5.0 V, AGND=DGND=0.0 V, V =+0.6 V and V =+2.6 V, unless otherwise specified.
A
DD
DD
RB
RT
TEST
CONDITIONS
TEST
LEVEL
SPT1175
TYP
PARAMETERS
MIN
MAX
UNITS
Dynamic Performance
Signal-To-Noise Ratio
f =1.0 MHz
f = 20 MSPS
S
I
I
V
44
43
46
45
39
dB
dB
dB
IN
f =3.58 MHz
IN
f =10 MHz
IN
Spurious Free
Dynamic Range
f = 20 MSPS
S
f =1.0 MHz
f =3.58 MHz
IN
I
I
44
41
47
44
dB
dB
IN
f =10 MHz
Differential Phase
Differential Gain
V
V
V
33
0.7
1.0
dB
Degrees
%
IN
NTSC 20 IRE Mod Ramp
f = 14.3 MSPS
S
Digital Inputs
Input Current, Logic High
Input Current, Logic Low
Pulse Width High (CLK)
Pulse Width Low (CLK)
Voltage, Logic High
V
DD
V
DD
= 5.25 V, V = V
DD
= 5.25 V, V = DGND
IL
I
I
IV
IV
I
1.0
1.0
µA
µA
ns
ns
V
IH
15
15
4.0
Voltage, Logic Low
I
1.0
V
Digital Outputs
Output Current, High
Output Current, Low
V
DD
V
DD
= 4.75 V
= 4.75 V
IV
IV
-1.1
3.5
mA
mA
Output Current, High Z
Voltage High
V
= 5.25 V,
= V
OE
IV
I
16
µA
V
DD
DD
4.0
Voltage Low
I
0.4
V
Power Supply Requirements
Analog Supply Voltage (AV
)
)
IV
IV
IV
I
+4.75
+4.75
-0.1
+5.0
+5.0
0.0
18
+5.25
+5.25
0.1
27
135
V
V
V
mA
mW
DD
Digital Supply Voltage (DV
Supply Voltage Difference
Supply Current
DD
(AV -DV
f =20 MSPS
S
)
DD
DD
Power Dissipation
I
90
TEST LEVEL CODES
TEST PROCEDURE
TEST LEVEL
All electrical characteristics are subject to the following
conditions:
100% production tested at the specified temperature.
I
100% production tested at T = +25 °C, and sample tested
II
A
at the specified temperatures.
Allparametershavingmin/maxspecificationsareguar-
anteed. The Test Level column indicates the specific
device testing actually performed during production
andQualityAssuranceinspection. Anyblanksectionin
the data column indicates that the specification is not
tested at the specified condition.
QA sample tested only at the specified temperatures.
III
Parameter is guaranteed (but not tested) by design and
characterization data.
IV
Parameter is a typical value for information purposes only.
V
100% production tested at T = +25 °C. Parameter is
VI
A
guaranteed over specified temperature range.
SPT1175
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3
Table I - Output Coding
INDEX
DIGITAL
OUTPUT
ANALOG INPUT (V)
0
0.6078125
0.6078125 ~ 0.6156260
0.6156250 ~ 0.6234375
....
00000000
00000001
00000010
....
1
V
V
=0.6 V
=2.6 V
RB
2
RT
....
123
124
125
....
1.5921875 ~ 1.6000000
1.6000000 ~ 1.6078125
1.6078125 ~ 1.6156250
....
01111111
10000000
10000001
....
1 LSB=7.8125 mV
254
255
2.5843750 ~2.5921875
2.5921875 ~
11111110
11111111
Figure 1A: Timing Diagram
V
(n)
IN
V
(n+3)
V
(n+1)
IN
IN
V
(n+2)
IN
V
IN
Clock
Data
Data (n-3)
Data (n-2)
Data (n-1)
Data (n)
t
d
Figure 1B: Tri-State Output Timing Diagram
50%
OE
50%
OE
2.5 V
90%
90%
V
2.5 V
2.5 V
OL
V
OL
10%
TeneL
220 Ω
TdisL
DUT
OE
50%
10%
50%
90%
50 pF
OE
V
V
OH
OH
2.5 V
TdisH
2.5 V
TeneH
SPT1175
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4
V
pinistobeshortedtotheV pin. Theself-biasinternal
RB
TYPICAL INTERFACE CIRCUIT
RBS
reference is not as stable over temperature and supply
variations as externally generated reference voltages but will
perform well in many commercial video applications.
The SPT1175 is an 8-bit analog-to-digital converter which
uses a two-step, ping-pong architecture to perform conver-
sions up to 20 MSPS. Figure 2 shows the typical interface
requirements when using the SPT1175 in normal operation.
Thefollowingsectionsdescribethefunctionandoperationof
the device.
Figure 3 - Reference Circuit Diagram
SPT1175
AV
DD
AGND
0 V
POWER SUPPLIES AND GROUNDING
5.0V
The SPT1175 operates from a single +5 V power supply.
AV
and DV
must be supplied from the same source
DD
DD
(analog +5 V) to prevent a latch-up condition due to power
supply sequencing. Each power supply pin should be by-
passed as closely as possible to the device. For optimal
performance, both the AGND and DGND should be con-
nected to the system's analog ground plane.
2.6 V
0.6 V
DIGITAL INPUTS AND OUTPUTS
The analog input is sampled and tracked on the first 'H' cycle
of the external clock and is held from the falling edge of CLK.
Theoutputremainsvalid(outputholdtime), andthenewdata
becomes valid (output delay time) after the rising edge of
CLK, delayed by 2.5 clock cycles. The clock input and output
enable input must be driven at CMOS-compatible levels.
ANALOG INPUT AND VOLTAGE REFERENCE
The SPT1175 input voltage range is V >V >V . Two
RT IN RB
reference voltages (V
and V ) are required for device
RT
RB
operation. These voltages may be generated externally or
the SPT1175's internal reference may be used.
EVALUATION BOARD
Inside the SPT1175, reference resistors are placed between
The EB1175 evaluation board is available to aid designers in
demonstrating the full performance of the SPT1175. This
board includes a reference circuit, clock driver circuit, output
data latches, and an on-board reconstruction DAC. An appli-
cation note describing the operation of the board is available.
Contact the factory for price and delivery.
AV and V
and between AGND and V so that V
RBS RTS
DD
RTS
and V
generate the 2.6 V and 0.6 V references respec-
RBS
tively. (See figure 3.) In order to utilize the internal self-bias
reference voltage, V is to be shorted with V and the
RTS
RT
Figure 2 - Typical Interface Circuit
10
10
+
+
10
10
+
13
14
15
16
17
18
19
20
21
22
23
24
12
CLK
DV
AV
DD
+
FB
+5
11
DV
R1
R9
DD
DD
DD
D7
+5 V
2k
Q1
10(MSB)
AV
V
-15
+
750
+15
C28
9
8
7
6
5
D6
D5
RTS
RT
C29
3
4
V
7
V
IN
75
R35
_U1
2
U1=Eleantec, EL2030
U2=OP.07
+5 V
D1
D4
AV
V
DD
D1=D2=RCA, SK9091
Q1=Q2=2N2222A
Outputs
R37
750
D3
IN
FR=FairRite, 2743001111
All capacitors are 0.01 µF unless
otherwise specified.
750
R36
D2
AGND
AGND
D2
4
D1
_
2
R15
6
3 (LSB)
10 k
C58
+U2
D0
V
RBS
10
3
R6
C61
C8
C59
2
1
DGND
OE
V
RB
R10
7.5 k
C60
DGND
R13
200
R8
3-ST
EN
Q2
-5
2k
+5
750
R2
+5
NOTE: AV
DD
and DV
must be supplied from the same source (Analog +5 V)
DD
to prevent a latch-up condition due to power supply sequencing.
SPT1175
6/24/97
5
PACKAGE OUTLINES
24-Lead Plastic DIP
INCHES
MILLIMETERS
MIN MAX
5.84
K
SYMBOL
MIN
MAX
A
B
C
D
E
F
G
H
I
0.130
0.115
0.230
0.200
0.023
0.070
3.30
2.92
0.36
1.14
2.54
0.20
2.92
7.62
6.10
29.97
0.13
5.08
0.58
1.78
0.00
0.38
4.95
0.00
7.87
32.64
0.014
24
0.045
.100 typ
0.008
I
0.015
0.195
0.115
.30 typ
0.240
1
0.310
1.285
J
1.180
K
.005 typ
J
H
G
A
B
F
D
C
E
24-Lead SOIC
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
24
A
B
C
D
E
F
G
H
I
0.587
0.606
14.90
15.40
.050 typ
0.014
0.006
0.067
0.012
0.295
0.205
1.27 typ
0.35
I
H
0.022
0.012
0.089
0.028
0.327
0.220
0.55
0.30
2.25
0.70
8.30
5.60
0.15
1
1.70
0.30
7.50
5.20
A
F
B
C
D
G
E
SPT1175
6/24/97
6
PACKAGE OUTLINES
28-Lead PLCC
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
MAX
A
B
C
D
E
F
G
H
I
0.450
0.485
45°
0.456
0.495
11.43
12.32
45°
11.58
12.57
0.165
0.175
0.010
4.19
4.45
0.25
0.00
0.00
0.00
10.92
0.022 typ
0.18 typ
0.05 typ
0.039
.56 typ
4.57 typ
1.27 typ
0.99
0.430
C
Pin 1
H
Pin 1
BOTTOM
VIEW
G
I
TOP
VIEW
F
E
A
B
D
SPT1175
6/24/97
7
PIN FUNCTIONS
PIN ASSIGNMENTS
Name
Function
OE
DGND
DØ (LSB)
D1
DGND
Tri-State Output Enable
OE
Tri-State When
Enable When
Digital Ground
= DV
= DGND
,
OE
OE
DD
V
RB
V
RBS
DGND
D0
AGND
AGND
Digital Output Data (LSB)
Digital Output Data
D1-6
D7
D2
Digital Output Data (MSB)
Digital Supply
V
D3
DIP and
SOIC
IN
DV
DD
AV
DD
D4
CLK
CMOS Digital Clock Input
Analog Supply
V
D5
RT
AV
DD
V
D6
V
Internal Self-Biased Reference Top
RTS
RTS
Shorted with V (pin 17). Generates 2.6 V.
Reference Resistor Top Side
RT
AV
DD
D7 (MSB)
V
V
RT
IN
DV
DD
AV
DD
Analog Input
DV
DD
CLK
AGND
Analog Ground
V
Internal Self-Biased Reference Bottom
RBS
Shorted with V (pin 23). Generates 0.6 V.
RB
V
Reference Resistor Bottom Side
RB
5
D1
25 AGND
22 AGND
6
7
D2
D3
V
23
22 N/C
IN
N/C
D4
8
9
PLCC
AV
21
20
19
DD
D5 10
D6 11
V
V
RT
RTS
ORDERING INFORMATION
PART NUMBER
SPT1175ACN
TEMPERATURE RANGE
0 to +70 °C
PACKAGE TYPE
24L Plastic Dip
28L PLCC
SPT1175ACP
0 to +70 °C
SPT1175ACS
0 to +70 °C
24L SOIC
SPT1175ACU
+25 °C
Die*
*See the die specification for guaranteed electrical performance.
SPT1175
6/24/97
8
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