SPT7864SCR [CADEKA]
10-BIT, 40 MSPS A/D CONVERTER; 10位， 40 MSPS A / D转换器
| 型号： | SPT7864SCR |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 10-BIT, 40 MSPS A/D CONVERTER |
| 文件： | 总8页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7864
10-BIT, 40 MSPS A/D CONVERTER
TECHNICAL DATA
NOVEMBER 20, 2001
FEATURES
APPLICATIONS
•40 MSPS maximum sample rate
•9.5 effective number of bits at ƒ IN = 10 MHz and
ƒS = 40 MSPS
• Video imaging
• Medical imaging
• Radar receivers
• IR imaging
• 2V P-P full-scale input range
•Differential input 2.5 V common mode
•Internal or external voltage reference
•Common-mode voltage reference output
•+3 V / +5 V digital output logic compatibility
•+5 V analog power supply
• Digital communications
•Sleep mode power dissipation: 55 mW
GENERAL DESCRIPTION
processing technologies to achieve its advanced perfor-
mance. Inputs and outputs are TTL/CMOS compatible to
interface with TTL/CMOS logic systems. Output data for-
mat is offset binary.
The SPT7864 is a 10-bit, 40 MSPS analog-to-digital con-
verter with low power dissipation at only 395 mW typical at
40 MSPS with a power supply of +5.0V.The digital outputs
are +3 V or +5 V, and are user selectable. The SPT7864 The SPT7864 is available in a 28-lead SSOP package
has incorporated proprietary circuit design and CMOS over the commercial temperature range.
BLOCK DIAGRAM
VDD GND
Sleep
VCM
Bias
Cell
Bandgap
Reference
EXT/INT
REFH
REFL
Data
1
10-BIT
40 MSPS
ADC
OR
VIN
VIN
10
Output
THA
Latches
& Buffers
10
D0D9
2
CLK, CLK
GND OVDD
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C
SupplyVoltages
VDD ...................................................................... 6.0 V
OVDD .................................................................... 6.0 V
Output
Digital Outputs.............................. –0.3 V to VDD +0.7 V
Temperature
Input Voltages
Analog Input ................................. –0.3 V to VDD +0.7 V
CLK Input ..................................... –0.3 V to VDD +0.7 V
OperatingTemperature ............................... 0 to +70 °C
StorageTemperature ............................ –65 to +150 °C
Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical
applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, ƒS=40 MSPS, VREFH=3.0 V, VREFL=2.0 V, OVDD=3.0 V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7864
TYP
PARAMETERS
Resolution
MIN
MAX
UNITS
10
Bits
DC Accuracy
Differential Linearity Error (DLE)
@ +25 °C
full temperature
@ +25 °C
V
V
V
V
VI
±0.5
±0.75
±0.6
LSB
LSB
LSB
LSB
Integral Linearity Error (ILE)
No Missing Codes
full temperature
±1.0
Guaranteed
Analog Input
Input Voltage Range (Differential)
Input Common Mode (VCM
Input Capacitance
Input Bandwidth
Common Mode Rejection Ratio (CMRR)
V
IV
V
V
V
±1
2.5
2
V
V
pF
MHz
dB
)
2
3
98
50
Timing Characteristics
Conversion Rate
VI
IV
V
V
V
40
MSPS
clocks
ns
ns
ps (rms)
Pipeline Delay (Latency)
Output Delay (tD)
Aperture Delay Time (tAP
Aperture Jitter Time
6
7.5
1.5
15
)
Dynamic Performance
Effective Number of Bits (ENOB)
ƒIN = 10 MHz, ƒCLK = 40 MSPS
25 °C
0 °C to +70 °C
I
IV
9.3
9.3
9.5
9.5
Bits
Bits
Signal-to-Noise Ratio (SNR)
ƒIN = 10 MHz, ƒCLK = 40 MSPS
25 °C
0 °C to +70 °C
I
IV
58
57
59
59
dB
dB
Total Harmonic Distortion (THD)
ƒIN = 10 MHz, ƒCLK = 40 MSPS
25 °C
0 °C to +70 °C
I
IV
–71
–71
–66
–65
dB
dB
Signal-to-Noise and Distortion (SINAD)
ƒIN = 10 MHz, ƒCLK = 40 MSPS
25 °C
0 °C to +70 °C
I
IV
57
57
59
59
dB
dB
Spurious Free Dynamic Range (SFDR)
ƒIN = 10 MHz, ƒCLK = 40 MSPS
25 °C
0 °C to +70 °C
I
IV
70
68
73
71
dB
dB
SPT7864
2
11/20/01
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, ƒS=40 MSPS, VREFH=3.0 V, VREFL=2.0 V, OVDD=3.0 V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7864
TYP
PARAMETERS
MIN
MAX
UNITS
Power Supply Requirements
V
DD Voltage (Analog Supply)
IV
IV
VI
VI
4.75
2.7
5.0
3.0/5.0
74
5.25
5.25
V
V
mA
mA
OVDD Voltage (Output Supply)
VDD Current
OVDD Current
8
Power Dissipation
External Voltage Reference
Internal Voltage Reference
Sleep Mode Power Dissipation
External Voltage Reference
Internal Voltage Reference
Power Supply Rejection Ratio (PSRR)
VI
VI
387
395
417
425
mW
mW
VI
VI
V
45
55
45
47
56
mW
mW
dB
Internal References
Common Mode Voltage Reference (VCM) IO = –1 µA
Common Mode Voltage Tempco
Output Impedance (VCM
VI
V
V
2.4
2.5
100
2
2.6
V
ppm/°C
kΩ
)
Reference Low Output Voltage (VREFL
Reference High Output Voltage (VREFH
)
(EXT/INT) = 0
(EXT/INT) = 0
VI
VI
1.95
2.95
2.0
3.0
2.05
3.05
V
V
)
External References
Reference Low Input Voltage Range
Reference High Input Voltage Range
(EXT/INT) = 1
(EXT/INT) = 1
IV
IV
1.7
2.7
2.0
3.0
2.3
3.3
V
V
Digital Outputs
Output Voltage High
Output Voltage Low
IO = –2 mA
IO = 2 mA
VI
VI
85% OVDD 90% OVDD
0.2
OVDD
0.4
V
V
Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VI
VI
VI
VI
80% VDD
V
V
µA
µA
20% VDD
±100
±100
Clock Inputs
Clock Inputs High Voltage
Clock Inputs Low Voltage
Clock Inputs High Current
Clock Inputs Low Current
VI
VI
VI
VI
2
5
0.4
±115
±115
V
V
µA
µA
TEST LEVEL CODES
TEST LEVEL TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested
at the specified temperatures.
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection. Any
blank section in the data column indicates that the
specification is not tested at the specified
condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and
characterization data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
SPT7864
3
11/20/01
TYPICAL PERFORMANCE CHARACTERISTICS
DLE Versus Sample Rate
ILE Versus Sample Rate
0.7
0.6
0.5
0.4
0.3
0.2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.0
IN = 1 kHz
IN = 1 kHz
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.5
0.6
0.7
30
40
50
60
70
30
40
50
60
70
Sample Rate (MSPS)
Sample Rate (MSPS)
DLEVersusTemperature
ILEVersusTemperature
0.7
0.6
0.5
0.4
0.3
0.2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.1
0.0
0.1
0.2
0.3
0.4
IN = 1 kHz
S = 40 MSPS
IN = 1 kHz
S = 40 MSPS
0.5
0.6
0.7
0.5
0.6
0.7
20
0
20
40
80
20
0
20
Temperature (Degrees C)
40
80
60
60
Temperature (Degrees C)
SNR, SINAD, –THD, SFDR Versus Sample Rate
SNR, SINAD, –THD, SFDR VersusTemperature
80
75
70
65
60
80
IN = 10 MHz
SFDR
THD
75
70
65
60
SFDR
THD
SNR
SNR
SINAD
SINAD
55
50
45
55
50
45
S = 40 MHz
IN = 10 MHz
30
40
Sample Rate (MSPS)
25
50
35
45
55
60
20
20
Temperature (Degrees C)
0
40
60
80
SPT7864
4
11/20/01
Figure 1 –Typical Interface Circuit
OR
D9
Sleep
Sleep
(MSB)
VCM
T1
D8
D7
D6
D5
D4
D3
D2
D1
D0
AIN
VIN
0.1
RT1
SPT7864
10
+
50 W
VIN
Mini-Circuits
T16T or
T11T
Ext
+A5
EXT/INT
REFL
(LSB)
+
0.1
REFH
10
+
0.1
10
0.1
0.1
10
Buffer
RT2
50 W
+D3/5
+
+
+D3/5
DGND
10
+A5
+A3/5
50 W
AGND
AGND
Ferrite Bead
1 kW
1 kW
+A5
T2
CLKIN
TYPICAL INTERFACE CIRCUIT
Circuits T1-6T or T1-1T. Proper termination of the input is
important for input signal purity.A small capacitor (typically
68 pF) across the inputs attenuates kickback noise from
REFERENCES
The SPT7864 has a differential analog input. The input the sample-and-hold. A small capacitor (1 nF) between
range is determined by the voltages VIN and VIN applied to VCM and ground has also been proven to be advanta-
reference pins REFH and REFL respectively, and is equal geous.
to ±(VIN–VIN). Externally generated reference voltages
If a DC-coupled, single-ended input is wanted, a solution
connected to REFH and REFL should be symmetric
based on operational amplifiers, as shown in figure 2, is
around 2.5 V. The input range can be defined between
usually preferred.The AD8138 is suggested for low distor-
±0.6 V and ±1.5 V. An internal reference exists, providing
tion and video bandwidth. Lower cost operational amplifi-
reference voltages at pins REFH and REFL equal to +3.0 V
ers may be used if the demands are less strict.
(VREFH) and +2.0 V (VREFL). These can be connected to
REFH and REFL by connecting pin EXT/INT to GND. The
references should be bypassed as close to the converter
pins as possible using 100 nF capacitors in parallel with
smaller capacitors (e.g. 220 pF) to ground.
Figure 2 – DC-Coupled, Single-Ended to Differential
Conversion (power supplies and bypassing
not shown)
51 W
ANALOG INPUT
470 W
AD8138
Input
470 W
The input of the SPT7864 can be configured in various
ways, dependent upon whether a single-ended or differen-
tial, AC- or DC-coupled input is wanted.
Offset
ADC
51 W
AD8138
100 W
V
IN
Analog
In
15 pF
100 W
V
IN
AC-coupled input is most conveniently implemented using
a transformer with a center-tapped secondary winding.
The center tap is connected to the VCM node, as shown in
figure 1.In order to obtain low distortion, it is important that
the selected transformer does not exhibit core saturation
at full scale. Excellent results are obtained with the Mini-
51 W
51 W
AD8138
470 W
470 W
470 W
SPT7864
5
11/20/01
DIFFERENTIAL CLOCK INPUT
ates from 50%, every second stage has a shorter time for
settling; thus it operates less accurately, causing degrada-
tion of SNR.
The SPT7864 clock can be driven differentially or single-
ended.When driven differentially, CLK and CLK accommo-
date differential sinusodial signals centered around VDD/2. In order to preserve accuracy at high input frequency, it is
The peak-to-peak value should be 0.8 V. In order to pre- important that the clock have low jitter and steep edges.
serve accuracy at high input frequency, it is important that Rise/fall times should be kept shorter than 2 ns whenever
the clock have low jitter.The differential clock input is made possible. Overshoot should be minimized. Low jitter is es-
to allow a low-jitter clock design. To ensure low jitter, the pecially important when converting high-frequency input
differential input should be a pure sine wave with low white signals. Jitter causes the noise floor to rise proportionally
noise floor.
to input signal frequency.Jitter may be caused by crosstalk
on the PCB. It is therefore recommended that the clock
trace on the PCB be made as short as possible.
SINGLE-ENDED CLOCK INPUT
For single-ended operation, the CLK node is internally
biased to 1.5 V, and should externally be decoupled to
DIGITAL OUTPUTS
ground by a capacitor. A CMOS logic level clock (5 V or The digital output data appears in offset binary code at
3 V) is applied at the CLK node. (To get an inverted clock CMOS logic levels. Full-scale negative input results in out-
input, CLK should be decoupled and the clock signal ap- put code 000...0. Full-scale positive input results in output
plied at the CLK node). The duty cycle of the clock should code 111...1.Output data are available 6 clock cycles after
be close to 50%. Consecutive pipeline stages in the ADC the data are sampled. The analog input is sampled one
are clocked in antiphase. With a 50% duty cycle, every aperture delay (tAP) after the high-to-low clock transition.
stage has the same time for settling. If the duty cycle devi- Output data should be sampled as shown in the timing dia-
gram (figure 5). The OR pin is an out-of-range pin; if the
outputs go either over or under range, OR is set high.
Figure 3 – Driving Differential Inputs with a
PCB LAYOUT AND DECOUPLING
Differential Configuration
A well designed PCB is necessary to get good spectral
V
IHD
purity from any high-performance ADC. A multilayer PCB
with a solid ground plane is recommended for optimum
performance. If the system has a split analog and digital
ground plane, it is recommended that all ground pins on
the ADC be connected to the analog ground plane.It is our
experience that this gives the best performance. The
power supply pins should be bypassed using 100 nF
surface mounted capacitors as close to the package pins
as possible. Analog and digital supply pins should be
separately filtered.
V
ID
V
ICM
V
ILD
Figure 4 – Driving Differential Inputs with a
Single-Ended Configuration
V
IH
V
ICM
V
IL
Figure 5 –Timing Diagram
N
N+1
N1
N+2
N+3
AIN
Clock
Clock
tD
tAP
tH
Data
Data
N1
Data
N+1
Data
N
Data
N+2
SPT7864
6
11/20/01
PACKAGE OUTLINE
28-Lead SSOP
INCHES
MILLIMETERS
28
SYMBOL
MIN
MAX
0.413
0.008
MIN
MAX
10.50
0.20
A
B
0.390
0.002
9.90
0.05
I
H
C
D
E
F
G
H
I
0.026 typ
0.65 BSC
0.009
0.004
0.065
0.022
0.291
0.197
0.015
0.010
0.073
0.037
0.323
0.220
0.22
0.09
1.65
0.55
7.40
5.00
0.38
0.25
1.85
0.95
8.20
5.60
1
A
F
B
C
D
H
G
E
SPT7864
7
11/20/01
PIN ASSIGNMENTS
PIN FUNCTIONS
Name Function
GND
VDD
Analog ground
1
2
3
28
27 D1
GND
VDD
D0
Analog +5 V
OGND
OVDD
REFL
Output ground
Supply voltage for digital outputs 3 V/5 V
26
25
24
D2
D3
D4
REFL
REFH
Reference pin low, input for external
reference, bypass with capacitor (10 µF)
when internal reference is selected.
4
5
6
7
EXT/INT
VCM
REFH
Reference pin high, input for external
reference, bypass with capacitor (10 µF)
when internal voltage is selected.
23 OGND
SPT7864
28L SSOP
22
OVDD
GND
VCM
VIN
2.5 V common mode voltage reference output
Non-inverted analog input
Inverted analog input
21 OGND
8
9
VDD
VIN
VIN
20
OVDD
CLK
CLK
Clock input pin
Complement of clock input pin, internally
biased to 1.5 V; if single-ended clock is used,
bypass to GND with 10 µF
19
18
VIN 10
D5
D6
11
12
13
14
Sleep
CLK
D0–D9
Digital outputs; D0 = LSB; 3 V/5 V compatible
Out-of-range bit; 3 V/5 V compatible
17
16
15
D7
OR
D8
EXT/INT EXT/INT = 1, external reference used; internal
reference powered down
CLK
OR
D9 (MSB)
EXT/INT = 0, internal reference used;
internally pulled down
Sleep
Sleep = 1, normal operation; internally pulled
up
Sleep = 0, powered-down mode
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGETYPE
SPT7864SCR
0 to +70 °C
28L SSOP
SPT7864
8
11/20/01
相关型号：
SPT7866SIR
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO28, SSOP-28
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明