SPT9693 [CADEKA]
WIDE INPUT VOLTAGE, JFET COMPARATOR; 宽广的输入电压，比较器JFET
| 型号： | SPT9693 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | WIDE INPUT VOLTAGE, JFET COMPARATOR |
| 文件： | 总10页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT9693
WIDE INPUT VOLTAGE, JFET COMPARATOR
TECHNICAL DATA
MARCH 1, 2001
FEATURES
APPLICATIONS
• Common mode range –3.0 to +8.0 V
• Low input bias current <100 pA
• Propagation delay 1.5 ns (max)
• Low offset ±25 mV
• Automated test equipment
• High-speed instrumentation
• Window comparators
• High-speed timing
• Low feedthrough and crosstalk
• Differential latch control
• Line receivers
• High-speed triggers
• Threshold detection
• Peak detection
GENERAL DESCRIPTION
The SPT9693 is a high-speed, wide common mode volt-
age, JFET input, dual comparator. It is designed for appli-
cations that measure critical timing parameters in which
wide common mode input voltages of –3.0 to +8.0 V are
required. Propagation delays are constant for overdrives
greater than 50 mV.
buffers in most applications. The device has differential
analog inputs and complementary logic outputs com-
patible with ECL systems. Each comparator has a
complementary latch enable control that can be driven by
standard ECL logic.
The SPT9693 is available in 20-contact LCC and 20-lead
PLCC packages over the commercial temperature range.
It is also available in die form.
JFET inputs reduce the input bias currents to the
nanoamp level, eliminating the need for input drivers and
BLOCK DIAGRAM
Q
Q
Q
Q
GND
B
A
A
B
B
GND
LE
LE
A
B
B
LE
LE
A
A
N/C
AV (B)
N/C
EE
AV (B)
AV (A)
CC
EE
AV (A) IN
+IN
+IN
IN
B
CC
A
A
B
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages (Measured to GND)
Positive Supply Voltage (AVCC) ............ –0.5 to +11.0 V
Negative Supply Voltage (AVEE) ........... –11.0 to +0.5 V
Output
Output Current ................................................... 30 mA
Temperature
Input Voltages
Operating Temperature, ambient................ 0 to +70 °C
junction......................+150 °C
Lead Temperature, (soldering 60 seconds) ..... +300 °C
Storage Temperature............................ –65 to +150 °C
Input Common Mode Voltage ................–6 to +AVCC+1
Differential Input Voltage .................... –12.0 to +12.0 V
Input Voltage, Latch Controls ...................... –6 to 0.5 V
V
IN to AVCC Differential Voltage ............... –16 to +1.0 V
Note: 1. Operation at any Absolute Maximum Rating is not implied.See
Electrical Specifications for proper nominal applied conditions
in typical applications.Application of multiple maximum rating
conditions at the same time may damage the device.
VIN to AVEE Differential Voltage ...............+4 to +21.0 V
ELECTRICAL SPECIFICATIONS
TA = +25 °C, AVCC = +10 V, AVEE = –10.0 V, RL = 50 Ohm to –2 V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
PARAMETERS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Input Offset Voltage
V
IN (Common Mode) = 0
I
IV
–25
–25
0.0
0.0
+25
+25
mV
mV
TMIN<TA<TMAX
Offset Voltage Tempco
Input Bias Current
V
I
50
±10
µV/°C
nA
T
MIN<TA<TMAX
VIN (Common Mode) = –3 to +7 V
MIN<TA<TMAX
±100
±150
Input Bias Current
Input Offset Current
T
I
±50
nA
VIN (Common Mode) = +7 to +8 V
V
V
±1.0
±10
nA
nA
TMIN<TA<TMAX
Positive Supply Current (Dual)
Negative Supply Current (Dual)
AVCC=10 V
AVEE=–10.0 V
I
I
3
40
6
55
mA
mA
Positive Supply Voltage, AVCC
Negative Supply Voltage, AVEE
IV
IV
9.75
–9.75
10.0
–10.0
10.25
–10.25
V
V
Input Common Mode Range
Latch Enable
Common Mode Range
Differential Voltage Range
Open Loop Gain
Differential Input Resistance
Input Capacitance
Power Supply Sensitivity
Common Mode Rejection Ratio
I
–3.0
–2.0
+8.0
V
IV
I
V
V
V
V
I
IV
I
0
±10
V
V
52
2
1.0
60
60
55
430
dB
GΩ
pF
dB
dB
dB
50
45
TMIN<TA<TMAX
Dual
Power Dissipation
610
mW
Output High Level
Output Low Level
ECL 50 Ohms to –2 V
ECL 50 Ohms to –2 V
I
I
–.98
–1.95
–.70
–1.65
V
V
SPT9693
2
3/1/01
ELECTRICAL SPECIFICATIONS
TA = +25 °C, AVCC = +10 V, AVEE = –10.0 V, RL = 50 Ohm to –2 V, unless otherwise specified.
TEST
TEST
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
AC ELECTRICAL PARAMETERS
Propagation Delay1
Propagation Delay Tempco
Propagation Delay Skew (A vs B)
Delay Dispersion from
Input Direction
50 mV O.D., Slew 10 V/ns
IV
V
V
.75
1.25
2
100
50
1.50
ns
ps/ °C
ps
V
ps
Delay Dispersion from
Input Common Mode
V
60
ps
Latch Set-up Time
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
V
V
V
V
V
V
V
500
500
500
0
0.45
0.45
5
ps
ps
ps
ps
ns
ns
V/ns
50 mV O.D.
20% to 80%
20% to 80%
Fall Time
Slew Rate
1Valid for both high-to-low and low-to-high transitions
LEVEL TEST PROCEDURE
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
IV
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT9693
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TYPICAL PERFORMANCE CHARACTERISTICS
INPUT BIAS CURRENT vs COMMON MODE VOLTAGE
(+25 °C)
INPUT OFFSET VOLTAGE vs COMMON MODE VOLTAGE
(T=+25 °C)
100
+10.0
+6.0
10
+2.0
2.0
1.0
0.1
6.0
0.01
10.0
0.001
3.0
1.6
+0.8
+3.2
+5.6
+8.0
3.0
1.6
+0.8
+3.2
+5.6
+8.0
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
PROPAGATION DELAY TIME vs TEMPERATURE
DELAY DISPERSION vs INPUT PULSE WIDTH
50
40
30
20
10
1600
1500
1400
1300
1200
Slope 2 ps/ °C
0
+25
+50
+75
+100
+125
+150
0
500
1000
1500
2000
2500
3000
TEMPERATURE (°C)
INPUT PULSE WIDTH (ps)
SPT9693
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TYPICAL PERFORMANCE CHARACTERISTICS
RISE AND FALL OF OUTPUTS vs TIME CROSSOVER
HYSTERESIS vs DLATCH VOLTAGE
V Hysteresis (mV)
.90
50
40
30
20
10
1.10
1.30
1.50
1.70
1.90
VLEVLE
(mV)
30
20
10
0
10
20
30
1.1
1.5
1.9
TIME (ns)
2.3
2.7
3.5
PROPAGATION DELAY vs INPUT
OVERDRIVE VOLTAGE
PROPAGATION DELAY vs
COMMON MODE INPUT VOLTAGE
1500
1400
1300
1200
1100
1600
1500
1400
1300
1200
Input Slew Rates
= 1 V/ns
= 2 V/ns
= 5 V/ns
50
100
150
200
(mV)
250
300
350
400
4
2
0
+2
+4
+6
+8
V
OD
V
, cm (V)
IN
SPT9693
5
3/1/01
GENERAL INFORMATION
Single-channel operation can be accomplished by floating
all pins (including the ground and supply pins) of the un-
used comparator. Power dissipation during single-channel
operation is 50% of the dissipation during dual-channel
operation.
The SPT9693 is an ultrahigh-speed dual voltage com-
parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems.The output stage is
adequate for driving terminated 50 ohm transmission This comparator offers the following improvements over
lines. existing devices:
The SPT9693 has a complementary latch enable control • Ultra low input bias current and input current offset
for each comparator. Both should be driven by standard • Common mode voltage of –3 to +8 V
ECL logic levels.
• Short propagation delays
• Excellent input and output rejection between
comparator channels
• Improved input protection reliability due to JFET input
stage design
A common mode voltage range of –3 V to +8 V is achieved
by a proprietary JFET input design, which requires a
separate negative power supply (AVEE).
The dual comparators have separate AVCC, AVEE, and
grounds for each comparator to achieve high crosstalk
rejection.
All of these combined features produce high-performance
products with timing stability and repeatability for large
system precision.
Figure 1 – Internal Function Diagram
Q
+IN
IN
+
PRE
AMP
ECL
OUT
LATCH
Q
REF
1
REF
2
CLK
BUF
V
AV
GND
LE
LE
CC
EE
SPT9693
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3/1/01
TYPICAL INTERFACE CIRCUIT
techniques must be employed to prevent ringing on the
output waveform. Also, the microstriplines must be termi-
nated at the far end with the characteristic impedance of
the line to prevent reflections. All supply voltages should
be decoupled with high-frequency capacitors as close to
the device as possible. If using the SPT9693 as a single
comparator, the outputs of the inactive comparator can be
grounded, left open or terminated with 50 ohms to –2 V. All
outputs on the active comparator, whether used or un-
The typical interface circuit using the comparator is shown
in figure 2. Although it needs few external components
and is easy to apply, there are several conditions that
should be noted to achieve optimal performance.The very
high operating speeds of the comparator require careful
layout, decoupling of supplies, and proper design of trans-
mission lines.
Since the SPT9693 comparator is a very high-frequency used, should have identical terminations to minimize
and high-gain device, certain layout rules must be followed ground current switching transients.
to avoid oscillations. The comparator should be soldered
All ground pins should be connected to the same ground
to the board with component lead lengths kept as short as
plane to further improve noise immunity and shielding.
possible. A ground plane should be used, while the input
Unused outputs must be terminated with 50 ohms to
impedance to the part is kept as low as possible, to de-
ground.
crease parasitic feedback. If the output board traces are
longer than approximately half an inch, microstripline
Figure 2 – SPT9693 Typical Interface Circuit
Figure 3 – SPT9693 Typical Interface Circuit
with Hysteresis
Q Output
Q Output
Q Output
Q Output
VIN
+
VIN
+
VRef
LE
VRef
LE
LE
LE
RL
50 W
R
L
RL
50 W
RL
50 W
50 W
1.3 V
0.1 µF
VC
» 5 V
VC
» 5 V
0.1 µF
.1 µF
550 W
550 W
2 V
2 V
2 V
Notes:
100 W 0 to 200 W
1) D1 = 1N5231B or 1N751 or equivalent.
2) D2 = 1N914 or equivalent.
Notes:
3) At no time should both inputs be allowed to float with power applied
to the device. At least one of the inputs should be tied to a voltage
within the common mode range (3.0 to +8.0 V) to prevent possible
damage to the device. Additional protection diodes D2 should be used
on the inputs if there is the possibility of exceeding the absolute
maximum ratings.
1) D1 = 1N5231B or 1N751 or equivalent.
2) D2 = 1N914 or equivalent.
3) At no time should both inputs be allowed to float with power applied
to the device. At least one of the inputs should be tied to a voltage
within the common mode range (3.0 to +8.0 V) to prevent possible
damage to the device. Additional protection diodes D2 should be
used on the inputs if there is the possibility of exceeding the absolute
maximum ratings.
SPT9693
7
3/1/01
TIMING INFORMATION
after the falling edge for the comparator to accept data.
After tH, the output ignores the input status until the latch
is strobed again. A minimum latch pulse width of tpL is
needed for strobe operation, and the output transitions
The timing diagram for the comparator is shown in figure
4. If LE is high and LE low in the SPT9693, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
occur after a time of tpLOH or tpLOL
.
The set-up and hold times are a measure of the time
required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry.
Input signals occurring before tS will be detected and held;
those occurring after tH will not be detected. Changes
between tS and tH may not be detected.
The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator out-
put after a time of tpdL or tpdH (Q or Q). The input signal
must be maintained for a time tS (set-up time) before the
LE falling edge and LE rising edge and held for time tH
Figure 4 – Timing Diagram
Latch Enable
50%
Latch Enable
tH
tpL
tS
Differential
Input Voltage
V
Ref ±VOS
VOD
V
IN
tpLOH
tpdL
Output Q
50%
50%
Output Q
tpdH
tpLOL
VIN+ = 300 mV, VOD = 150 mV
SWITCHING TERMS (Refer to figure 4)
tpdH INPUT TO OUTPUT HIGH DELAY – The propaga-
tion delay measured from the time the input signal
reaches the reference voltage (± the input offset
voltage) to the 50% point of an output LOW to HIGH
transition.
tH
MINIMUM HOLD TIME – The minimum time after
the negative transition of the Latch Enable signal
that the input signal must remain unchanged in order
to be acquired and held at the outputs.
tpL MINIMUM LATCH ENABLE PULSE WIDTH – The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
tpdL INPUT TO OUTPUT LOW DELAY – The propaga-
tion delay measured from the time the input signal
reaches the reference voltage (± the input offset
voltage) to the 50% point of an output HIGH to LOW
transition.
tS
MINIMUM SET-UP TIME – The minimum time
before the negative transition of the Latch Enable
signal that an input signal change must be present in
order to be acquired and held at the outputs.
tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY – The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
50% point of an output LOW to HIGH transition.
VOD VOLTAGE OVERDRIVE – The difference between
the differential input and reference input voltages.
tpLOL LATCH ENABLE TO OUTPUT LOW DELAY – The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition.
SPT9693
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3/1/01
PACKAGE OUTLINES
20-Contact Leadless Chip Carrier (LCC)
A
H
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
A
B
C
D
E
F
.040 typ
.050 typ
1.02 typ
1.27 typ
G
0.045
0.345
0.054
0.055
0.360
0.066
1.14
8.76
1.37
1.40
9.14
1.68
Bottom
View
Pin 1
B
C
.020 typ
0.51 typ
G
H
0.022
0.028
0.075
0.56
0.71
1.91
F
D
E
20-Lead Plastic Leadless Chip Carrier (PLCC)
A
G
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
B
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
.045 typ
.045 typ
1.14 typ
1.14 typ
Pin 1
N
0.350
0.385
0.350
0.385
0.042
0.165
0.085
0.025
0.015
0.026
0.013
0.356
0.395
0.356
0.395
0.056
0.180
0.110
0.040
0.025
0.032
0.021
0.050
0.330
8.89
9.78
8.89
9.78
1.07
4.19
2.16
0.64
0.38
0.66
0.33
9.04
10.03
9.04
10.03
1.42
4.57
2.79
1.02
0.64
0.81
0.53
1.27
8.38
TOP
VIEW
M
O
E
F
L
K
C
D
J
I
H
Pin 1
0.290
7.37
BOTTOM
VIEW
SPT9693
9
3/1/01
PIN ASSIGNMENTS
PIN FUNCTIONS
NAME
QA
FUNCTION
QA QA QB QB GNDB
3 20 19
Output A
2
1
QA
Inverted Output A
Ground A
GNDA
LEA
18 LEB
4
5
6
GNDA
LEA
Inverted Latch Enable A
Latch Enable A
LEB
17
LEA
AVCC(A)
AVEE(A)
AVCC(B)
AVEE(B)
–INA
+INA
+INB
–INB
LEB
Positive Supply Voltage (+10 V)
Negative Supply Voltage (–10 V)
Positive Supply Voltage (+10 V)
Negative Supply Voltage (–10 V)
Inverting Input A
16
LEA
TOP VIEW
LCC/PLCC
N/C
15 AVEE(B)
N/C
7
8
AVCC(B)
14
AVEE(A)
Noninverting Input A
Noninverting Input B
Inverting Input B
9
10
11
13
12
AVCC(A) INA +INA +INB INB
Inverted Latch Enabled B
Latch Enable B
LEB
GNDB
QB
Ground B
Inverted Output B
Output B
QB
N/C
Not Connected
ORDERING INFORMATION
PART NUMBER
SPT9693SCC
SPT9693SCP
SPT9693SCU
TEMPERATURE RANGE
0 to +70 °C
PACKAGE TYPE
LCC
PLCC
Die*
0 to +70 °C
+25 °C
*Please see the die specification for guaranteed electrical performance.
SPT9693
10
3/1/01
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