TMC3033KRC80 [CADEKA]
Triple Video D/A Converter 10 bit, 80 Msps; 三路视频D / A转换器10位， 80 Msps的
| 型号： | TMC3033KRC80 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Triple Video D/A Converter 10 bit, 80 Msps |
| 文件： | 总12页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.cadeka.com
TMC3033
Triple Video D/A Converter
10 bit, 80 Msps
Features
Description
• 10-bit resolution
• 80, 50, and 30 megapixels per second
• Sync and blank controls
The TMC3033 is a high-speed triple 10-bit D/A converter
especially suited for video and graphics applications.
It offers 10-bit resolution, TTL-compatible inputs, low
power consumption, and requires only a single +3.3 Volt
±5% power supply. It has single-ended current outputs,
SYNC and BLANK control inputs, and a separate current
source for adding sync pulses to the Green D/A converter
output. It is ideal for generating analog RGB from digital
RGB and driving computer display and video monitors.
Three speed grades are available: 30, 50, and 80 Msps.
• Sync on green D/A output
• 1.0V p-p video into 37.5Ω or 75Ω load
• Enhancement of ADV7122
– Internal bandgap voltage reference
– Double-buffered data for low distortion
• TTL-compatible inputs
• Low glitch energy
• Single +3.3 Volt ±5% power supply
The TMC3033 triple D/A converter is available in a 44-lead
plastic J-leaded PLCC and 48-lead plastic LQFP package.
It is fabricated on a sub-micron CMOS process with perfor-
mance guaranteed from 0°C to 70°C.
Applications
• Video signal conversion
– RGB
– YC C
B R
– Composite, Y, C
• Multimedia systems
• Image processing
• True-color graphics systems (1 billion colors)
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
Block Diagram
SYNC
BLANK
10
10 bit
D/A Converter
G
B
R
IO
IO
IO
9-0
9-0
9-0
G
B
R
10
10
10 bit
D/A Converter
10 bit
D/A Converter
COMP
CLK
R
REF
REF
+1.235V
Ref
V
65-3003-01
Rev. 1.0.0
TMC3033
PRODUCT SPECIFICATION
Functional Description
The TMC3033 is a low-cost triple 10-bit CMOS D/A
converter designed to directly drive computer CRT displays
and video transmission lines at pixel rates of up to 80 Msps.
It comprises three identical 10-bit D/A converters with
registered data inputs, common clock, and internal voltage
reference. An independent current source allows sync to be
added to the green D/A converter output.
D/A Outputs
Each D/A output is a current source. To obtain a voltage out-
put a resistor must be connected to ground. Output voltage of
the D/A converters depends upon this resistor, the reference
voltage, and the value of the gain-setting resistor connected
between R
and GND.
REF
Normally, a source termination resistor of 75 Ohms is con-
nected between the D/A current output pin and GND near
the D/A converter. A 75 Ohm coaxial cable may then be con-
nected with another 75 Ohm termination resistor at the far
end of the cable. This “double termination” presents the D/A
converter with a net resistive load of 37.5 Ohms.
Digital Inputs
All digital inputs are TTL-compatible. Data are registered on
the rising edge of the CLK signal. The analog output
changes tDO after the rising edge of CLK. There is one stage
of pipeline delay on the chip. The guaranteed clock rates of
the TMC3033 are 80, 50, and 30 MHz.
The TMC3033 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
SYNC and BLANK
desired range, the value of the resistor on R
increased.
should be
REF
SYNC and BLANK inputs control the output level
(Figure 1 and Table 1) of the D/A converters during CRT
retrace intervals. BLANK forces the D/A outputs to the
blanking level while SYNC turns off a separate current
source which is connected to the green D/A converter. This
connection adds a 40 IRE sync pulse to the D/A output and
brings that D/A output to 0.0 Volts during the sync tip.
SYNC and BLANK are registered on the rising edge of
CLK.
Voltage Reference
The TMC3033 has an internal bandgap voltage reference
of +1.235 Volts. An external voltage reference may be
connected to the V
pin, overriding the internal voltage
REF
reference. All three D/A converters are driven from the same
reference.
A 0.1µF capacitor must be connected between the COMP
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = LOW, data
inputs and the pedestal are disabled.
pin and V
to stabilize internal bias circuitry and ensure
DD
low-noise operation.
Power and Ground
The TMC3033 D/A converter requires a single +3.3 Volt
power supply. The analog (V ) power supply voltage
DD
should be decoupled to GND to reduce power supply
induced noise. 0.1µF decoupling capacitors should be placed
as close as possible to the power pins.
data: 660 mV max.
pedestal: 54 mV
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic distor-
tion or reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane for
best performance.
sync: 286 mV
65-3003-02
Figure 1. Nominal Output Levels
2
PRODUCT SPECIFICATION
TMC3033
Table 1. Output Voltage versus Input Code, SYNC, and BLANK
V
REF
= 1.235 V, R = 572 Ω, R = 37.5 Ω
REF L
Red and Blue D/As
Green D/A
RGB
9-0
(MSB...LSB)
11 1111 1111
11 1111 1110
11 1111 1101
•
SYNC
BLANK
V
SYNC
BLANK
V
OUT
OUT
X
X
X
•
1
1
1
•
0.7140
0.7134
0.7127
•
1
1
1
•
1
1
1
•
1.0000
0.9994
0.9987
•
•
•
•
•
•
•
•
10 0000 0000
01 1111 1111
•
X
X
•
1
1
•
0.3843
0.3837
•
1
1
•
1
1
•
0.6703
0.6697
•
•
•
•
•
•
•
•
00 0000 0010
00 0000 0001
00 0000 0000
xx xxxx xxxx
xx xxxx xxxx
X
X
X
X
X
1
1
1
0
0
0.0553
0.0546
0.0540
0.0000
0.0000
1
1
1
1
0
1
1
1
0
0
0.3413
0.3406
0.3400
0.2860
0.0000
Pin Assignments
G
G
G
G
G
G
G
G
G
7
39
38
37
36
35
34
33
32
31
30
29
R
V
1
2
3
4
5
6
7
8
9
REF
8
36
R
V
1
2
3
4
5
6
7
8
9
G
G
G
G
G
G
G
G
G
REF
REF
REF
1
2
3
4
5
6
7
8
9
35
34
33
32
31
30
29
28
9
COMP
COMP
10
11
12
13
14
15
16
17
IO
IO
V
R
G
IO
R
PLCC
LQFP
IO
G
OV
DD
TMC3033
TMC3033
DD
DD
V
DD
V
IO
B
GND
GND
CLOCK
NC
IO
B
BLANK
10
11
12
27
26
25
GND
GND
CLK
SYNC
V
BLANK
SYNC
DD
3
TMC3033
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number
Pin Name
Clock and Pixel I/O
CLK 29
PLCC
LQFP
Value
Description
26
TTL
Clock. The clock input is TTL-compatible and all pixel data
is registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid
reflection induced jitter, overshoot, and undershoot.
R
5, 4, 3, 2, 1, 47, 46, 45,
44, 43, 42, 44, 43, 42,
TTL
Red pixel data inputs. The Red digital input is TTL-
compatible and registered on the rising edge of CLK.
9-0
41, 40
41, 40, 39,
38, 37
G
15, 14, 13, 48, 9, 8, 7, 6,
12, 11, 10, 9, 5, 4, 3, 2, 1
8, 7, 6
TTL
TTL
Green pixel data inputs. The Green digital input is TTL-
compatible and registered on the rising edge of CLK.
9-0
B
9-0
28, 27, 26, 23, 22, 21,
25, 24, 23, 20, 19, 18,
22, 21, 20, 17, 16, 15,
Blue pixel data inputs. The Blue digital input is TTL-
compatible and registered on the rising edge of CLK.
19
14
Controls
SYNC
17
11
TTL
Sync pulse Input. Bringing SYNC LOW, turns off a 40
IRE (7.62 mA) current source which forms a sync pulse on
the Green D/A converter output. SYNC is registered on the
rising edge of CLK along with pixel data and has the same
pipeline latency as BLANK and pixel data. SYNC does not
override any other data and should be used only during
the blanking interval.
Since this is a single-supply D/A and all signals are
positive-going, sync is added to the bottom of the Green
D/A range. So turning SYNC OFF means turning the
current source ON. When a sync pulse is desired, the
current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC
should be connected to GND.
BLANK
16
10
TTL
Blanking Input. When BLANK is LOW, pixel inputs are
ignored and the D/A converter outputs are driven to the
blanking level. BLANK is registered on the rising edge of
CLK and has the same pipeline latency as SYNC.
Video Outputs
IO
36
35
33
32
0.714 Vp-p Red D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
R
IO
1 V p-p
Green D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
Sync pulses may be added to the Green D/A output.
G
IO
32
29
0.714 Vp-p Blue D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
B
4
PRODUCT SPECIFICATION
TMC3033
Pin Descriptions (continued)
Pin Number
Pin Name
PLCC
LQFP
Value
Description
Voltage Reference
V
38
39
35
+1.235 V
Voltage Reference output/input. An internal voltage
source of +1.235 Volts is output on this pin. An external
+1.235 Volt reference may be applied here which
REF
overrides the internal reference. Decoupling V
to GND
REF
with a 0.1µF ceramic capacitor is required.
R
36
572 Ω
Current-setting resistor. The full-scale output current of
REF
each D/A converter is determined by the value of the
resistor connected between R
and GND. The nominal
REF
value for R
REF
is found from:
R
REF
= 9.1( V /I ),
REF FS
but is optimized to be 572 Ω. I is the full-scale (white)
FS
output current (in amps) from an output without sync. Sync
current is 0.4 * I
.
FS
D/A full-scale (white) current may also be calculated from:
I
= V / R
FS
FS
L
Where V is the white voltage level and R is the total
FS
L
resistive load (in ohms) on each D/A converter. V is the
FS
blank to full-scale voltage.
COMP
37
34
0.1 µF
Compensation capacitor. A 0.1 µF ceramic capacitor
must be connected between COMP and V
internal bias circuitry.
to stabilize
DD
Power and Ground
V
18, 33, 34
30, 31
12, 30, 31
27, 28
+3.3 V
0.0 V
Power supply
Ground
DD
GND
Equivalent Circuits
V
DD
V
DD
p
Digital
Input
n
p
V
DD
n
OUT
GND
GND
27014C
27013B
Figure 2. Equivalent Digital Input Circuit
Figure 3. Equivalent Analog Output Circuit
5
TMC3033
PRODUCT SPECIFICATION
Equivalent Circuits (continued)
V
DD
p
p
R
REF
V
REF
27012B
GND
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
Power Supply Voltage
V
DD
(Measured to GND)
-0.5
7.0
V
Inputs
Applied Voltage (measured to GND)2
Forced Current3,4
-0.5
V
V
+ 0.5
V
DD
-10.0
10.0
mA
Outputs
Applied Voltage (measured to GND)2
-0.5
+ 0.5
V
DD
Forced Current3,4
-60.0
60.0
mA
Short Circuit Duration (single output in HIGH state to ground)
infinite
second
Temperature
Operating, Ambient
Junction
-20
110
150
300
220
150
°C
°C
°C
°C
°C
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
-65
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
6
PRODUCT SPECIFICATION
TMC3033
Operating Conditions
Parameter
Min
Nom
Max
3.465
30
Units
V
V
Power Supply Voltage
Conversion Rate
3.135
3.3
DD
f
S
TMC3033-30
TMC3033-50
TMC3033-80
Msps
Msps
Msps
ns
50
80
t
t
t
t
CLK Pulsewidth, HIGH
CLK Pulsewidth, LOW
Input Data Setup Time
Input Date Hold Time
5.2
5.2
3.6
2
PWH
PWL
s
ns
ns
ns
h
V
Reference Voltage, External
Compensation Capacitor
Output Load
1.0
1.235
0.1
1.5
V
REF
C
µF
C
L
R
37.5
Ω
V
V
Input Voltage, Logic HIGH
Input Voltage, Logic LOW
Ambient Temperature, Still Air
2.0
GND
0
V
V
IH
IL
A
DD
0.8
70
V
T
°C
Electrical Characteristics
Parameter
Conditions3
V = Max
DD
Min
Typ1
Max
Units
I
Power Supply Current2
DD
TMC3033-30
TMC3033-50
TMC3033-80
90
95
mA
132
PD
Total Power Dissipation2
V
DD
= Max
TMC3033-30
TMC3033-50
TMC3033-80
300
315
435
mW
R
C
Output Resistance
Output Capacitance
Input Current, HIGH
Input Current, LOW
100
kΩ
pF
µA
µA
µA
V
O
I
= 0mA
30
-1
O
OUT
I
I
I
V
V
= Max, V = 2.4V
IN
IH
DD
DD
= Max, V = 0.4V
IN
1
IL
V
REF
Input Bias Current
0
1.235
0
±100
REF
V
REF
V
OC
Reference Voltage Output
Output Compliance
Referred to V
DD
-0.4
+1.5
10
V
C
Digital Input Capacitance
4
pF
DI
Notes:
1. Values shown in Typ column are typical for V = +3.3V and T = 25°C.
DD
= Max and T = Min.
A
2. Minimum/Maximum values with V
DD
A
3. V
REF
= 1.235V, R
LOAD
= 37.5Ω, R = 572Ω
REF
7
TMC3033
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions2
Min
Typ1
10
1
Max
15
2
Units
ns
t
t
t
t
t
Clock to Output Delay
Output Skew
VDD = Min
D
ns
SKEW
R
Output Risetime
Output Falltime
10% to 90% of Full Scale
90% to 10% of Full Scale
to 3%/FS
3
4
ns
3
4
ns
F
Output Settling Time
15
ns
SET
Notes:
1. Values shown in Typ column are typical for V = +3.3V and T = 25°C.
DD
A
2. V
REF
= 1.235V, R
LOAD
= 37.5Ω, R
REF
= 572Ω.
System Performance Characteristics
Parameter
Conditions2
Min
Typ1
Max
Units
%/FS
%/FS
%
E
E
E
V
Integral Linearity Error
Differential Linearity Error
DAC to DAC Matching
Output Offset Current
V
V
V
V
, V
= Nom
= Nom
= Nom
±0.1
±0.1
7
±0.25
±0.25
10
LI
DD REF
, V
DD REF
LD
DM
OF
, V
DD REF
= Max, R, G, B = 000h
20
mA
DD
PSR
Power Supply Rejection
0.05
%/%
Notes:
1. Values shown in Typ column are typical for V = +3.3V and T = 25°C.
DD
A
2. V
REF
= 1.235V, R
LOAD
= 37.5Ω, R
REF
= 572Ω.
Timing Diagram
1/f
S
t
t
PWL
PWH
CLK
t
H
t
S
PIXEL DATA
& CONTROLS
DataN
DataN+1
DataN+2
3%/FS
90%
10%
t
D
t
SET
t
t
F
R
OUTPUT
50%
65-3003-03
8
PRODUCT SPECIFICATION
TMC3033
Applications Discussion
Figure 4 illustrates a typical TMC3033 interface circuit.
In this example, an optional 1.2 Volt bandgap reference is
the power supply for the TMC3033 is the same as that of
the system's digital circuitry, power to the TMC3033
should be decoupled with 0.1µF and 0.01µF capacitors
and isolated with a ferrite bead.
connected to the V
output, overriding the internal volt-
REF
age reference source.
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
Grounding
It is important that the TMC3033 power supply is well-
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video sig-
nals at the output of the circuit. The TMC3033 has separate
analog and digital circuits. To keep digital system noise from
the D/A converter, it is recommended that power
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the TMC3033, the
voltage reference, or the analog outputs. Capacitive cou-
pling of digital power supply noise from this layer to the
TMC3033 and its related analog circuitry can have an
adverse effect on performance.
supply voltages (V ) come from the system analog power
DD
source and all ground connections (GND) be made to the
analog ground plane. Power supply pins should be individu-
ally decoupled at the pin.
5. CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board lay-
out. Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following
suggestions when doing the layout:
Related Products
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1. Keep the critical analog traces (V , COMP,
, I
IO , IO , IO ) as short as possible and as far as possi-
REF REF
R
G
B
ble from all digital signals. The TMC3033 should be
located near the board edge, close to the analog output
connectors.
2. The power plane for the TMC3033 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the V
pins. If
DD
+3.3V
10µF
0.1µF
Red
O
V
GND
DD
Z
=75Ω
75Ω
75Ω
75Ω
IO
IO
IO
R
G
B
RED PIXEL
INPUT
Green
R
75Ω
75Ω
75Ω
9-0
Z
=75Ω
O
Blue
GREEN PIXEL
INPUT
Z
=75Ω
G
O
9-0
TMC3033
Triple 10-bit
BLUE PIXEL
INPUT
B
9-0
D/A Converter
+3.3V
COMP
0.1µF
572Ω
3.3kΩ
V
R
REF
CLOCK
SYNC
BLANK
CLK
SYNC
BLANK
0.1µF
LM185-1.2
(Optional)
REF
65-3033-04
Figure 4. Typical Interface Circuit
9
TMC3033
PRODUCT SPECIFICATION
Mechanical Dimensions – 44-Lead PLCC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Min.
Max.
Min.
Max.
2. Corner and edge chamfer (J) = 45°
A
.165
.090
.020
.013
.026
.685
.650
.180
.120
—
4.19
2.29
.51
4.57
3.05
—
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
A1
A2
B
.021
.032
.695
.656
.33
.53
B1
.66
.81
D/E
D1/E1
D3/E3
e
17.40
16.51
17.65
16.66
3
2
.500 BSC
.050 BSC
.042 .056
12.7 BSC
1.27 BSC
1.07 1.42
J
ND/NE
N
11
44
11
44
ccc
—
.004
—
0.10
E
E1
J
D
D1
D3/E3
B1
J
e
A
A1
– C – LEAD COPLANARITY
ccc C
B
A2
10
PRODUCT SPECIFICATION
TMC3033
Mechanical Dimensions – 48-Lead LQFP Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
A
.055
.001
.053
.006
.346
.268
.063
.005
1.40
.05
1.60
.15
A1
A2
B
1.35
.17
8.8
.057
.010
.362
.284
1.45
.27
9.2
7.2
3. Pin 1 identifier is optional.
7
8
2
4. Dimension ND: Number of terminals.
D/E
D1/E1
e
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
6.8
.019 BSC
.50 BSC
7. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
L
.017
.029
.45
.75
6
4
5
N
48
12
48
12
ND
α
ccc
0°
7°
0°
7°
.004
0.08
8.
To be determined at seating place —C—
D
D1
e
PIN 1
IDENTIFIER
E
E1
C
α
L
0.063" Ref (1.60mm)
See Lead Detail
Base Plane
A2
A
B
-C-
Seating Plane
LEAD COPLANARITY
ccc
A1
C
11
TMC3033
PRODUCT SPECIFICATION
Ordering Information
Conversion
Temperature
Range
Package
Marking
Product Number
TMC3033R2C30
TMC3033R2C50
TMC3033R2C80
TMC3033KRC30
TMC3033KRC50
TMC3033KRC80
Rate (Msps)
30 Msps
50 Msps
80 Msps
30 Msps
50 Msps
80 Msps
Screening
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Package
T = 0°C to 70°C
A
44-Lead PLCC
44-Lead PLCC
44-Lead PLCC
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
3033R2C30
3033R2C50
3033R2C80
3033KRC30
3033KRC50
3033KRC80
T = 0°C to 70°C
A
T = 0°C to 70°C
A
T = 0°C to 70°C
A
T = 0°C to 70°C
A
T = 0°C to 70°C
A
3/3/99 0.0m 001
Stock#DS30003033
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