PRN299 [CALMIRCO]
POSITIVE/POEUDO ECL(PECL)CLOCK TERMINATION NETWORK; 正/ POEUDO ECL （ PECL ）时钟终端网络
| 型号： | PRN299 |
| 厂家： | 
CALIFORNIA MICRO DEVICES CORP |
| 描述： | POSITIVE/POEUDO ECL(PECL)CLOCK TERMINATION NETWORK |
| 文件： | 总3页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CALIFORNIA MICRO DEVICES
PRN299
POSITIVE / PSEUDO ECL (PECL) CLOCK TERMINATION NETWORK
Features
Stable resistor network
Applications
PECL clock termination
Reduces power dissipation on the clock lines
Ideal for high-speed clock termination
Reduces board space by 70% vs. 1206 discretes
and component count by more than 50%
Application Note
High speed microprocessors line Intels Pentium/P6, Apple PowerPC, SPARC and other CISC and RISC based systems need
well-controlled and precise clock signals to maintain a synchronous systems. The fast edge rated clock signals will exhibit
transmission line effects on the clock lines resulting in undershoots and overshoots. The integrated PECL termination is
designed to suppress the undershoots and overshoots on the clock lines. The PECL RC terminator dissipates very low power
compared to the resistor termination network.
Why thin.film R networks? The PECL termination is an integrated R network fabricated on a silicon substrate using
advanced thin film technology. This will have a fixed time constant and will not create additional skew on the clock lines. It
has a low parasitic inductance compared to discrete and conventional thick film R terminators and provide effective termination
at high frequencies.
S TA N D A R D VA LU E S
S C H E M A TIC D IA G R A M
R1 (Ω
)
± 1%
R2 (Ω
)
± 1%
R3 (Ω
)
± 1%
50
50
46.4
S TA N D A R D P A R T O R D E R IN G IN F O R M A TIO N
Package
Ordering Part Num ber
Pins
Style
Part Marking
3
SOT-23
PRN299
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved.
PAC VGA200 is a trademark of California Micro Devices Corp.
3/00
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
PRN299
A B S O LU TE M A X IM U M R A TIN G S
Param eter
Rating
GND-0.5, + 6.0
100
Unit
V
VCC1, VCC2 , VCC3 & VCC4 supply voltage
Diode D1 forward current
DC voltage at inputs:
VIDEO_1, VIDEO_2, VIDEO_3
TERM_1, TERM_2, TERM_3
DDC_IN1, DDC_IN2
uA
V
GND-0.5, VCC1+ 0.5
-6.0, + 6.0
V
V
GND-0.5, VCC2+ 0.5
GND-0.5, VCC3+ 0.5
GND-0.5, VCC4+ 0.5
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
Temperature:
V
V
Storage
-40 to + 150
0 to + 70
1.0
oC
oC
W
Operating Ambient
Package power dissipation
E LE C TR IC A L O P E R A TIN G C H A R A C TE R IS TIC S
( o ve r o p e r a t in g c o n d it io n s u n le s s s p e c if ie d o t h e r w is e )
Sym bol Param eter
Conditions
MIN
TYP
MAX
10
UNIT
uA
ICC1
VCC1 supply current
VCC1 = 5V; VIDEO inputs at VCC1 or GND
VCC2 = VCC3 = 5V
ICC2, 3
ICC4
VCC2, VCC3 supply current
VCC4 supply current
10
uA
VCC4 = 5V; SYNC inputs at GND or VCC4
;
10
uA
PWR_UP pin at VCC4; SYNC outputs unloaded
VCC4 = 5V; SYNC inputs at 3.0V; PWR_UP
pin at VCC4; SYNC outputs unloaded
VCC4 = 5V; PWR_UP input at GND; SYNC
outputs unloaded
200
uA
uA
10
VBIAS
RT
VBIAS open circuit voltage
VIDEO termination resistance
RT resistance matching
Logic High input voltage1
Logic Low input voltage1
Logic High output voltage1
Logic Low output voltage1
Resistor value
No external current drawn from VBIASpin
VCC4-0.8
V
Ω
71.25
2.0
75
78.75
1
2
%
VIH
VCC4 = 5.0V
V
VIL
VCC4 = 5.0V
0.8
V
VOH
VOL
IOH = -4mA, VCC4 = 5.0V
IOL = 4mA, VCC4 = 5.0V
PWR_UP, VCC3 = 5.0V
VCC2 = 3.0V
4.4
V
0.4
2
V
Rb, Rp
0.5
0.5
1
MΩ
MΩ
R
c
VCC2 pull-down resistor
Input current
1.5
3
IN
VIDEO inputs
V
CC1 = 5V; VIN = VCC1 or GND
CC4 = 5V; VIN = VCC4 or GND
(VCC2 - VDDC_IN) < 0.4V; VDDC
± 1
± 1
10
µA
µA
µA
µA
V
HSYNC, VSYNC inputs
OFF state leakage current, level
shifting NFET
V
IOFF
_ = VCC2
OUT
(VCC2 - VDDC_OUT) < 0.4V; VDDC_IN= VCC2
VCC2 = 2.5V; VS = GND, IDS = 3mA
10
VON
Voltage drop across level
shifting NFET when turned ON
0.15
3
C
IN
Input capacitance
VIDEO_1, VIDEO_2, VIDEO_3
VCC1 = 5.0V; VIN = 2.5V; measured at 1MHz
VCC1 = 2.5V; VIN = 1.25V; measured at 1MHz
4.0
4.5
8
pF
tPLH
SYNC drivers L-H propagation delay CL = 50 pF; VCC = 5V; Input tr and tf < 5ns
SYNC drivers H-Lpropagation delay CL = 50 pF; VCC = 5V; Input tr and tf < 5ns
SYNC drivers output rise & fall times CL = 50 pF; VCC = 5V; Input tr and tf < 5ns
12
12
ns
ns
ns
kV
tPHL
tr, tf
VESD
8
7
ESD withstand voltage2, 3
VCC1 = VCC3 = VCC4 = 5V
± 8
Note 1: These parameter applies only to the HSYNC and VSYNC channels.
Note 2: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC3 and VCC4 must be bypassed
to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins
are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD
protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
Note 3: This parameter is guaranteed by design and characterization.
©2000 California Micro Devices Corp. All rights reserved.
3/00
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
2
CALIFORNIA MICRO DEVICES
PRN299
Typical Connection Diagram
A resistor may be necessary between the VCC3 pin and ground if protection against a stream of ESD pulses is required while the
PAC VGA200 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into
the VCC3 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD
repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PAC VGA200 is in the power-up
state, an internal discharge resistor is connected to ground via an FET switch for this purpose.
For the same reason, VCC1 and VCC4 may also require bypass capacitor discharging resistors to ground if there are no other
components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75R resistors is not connected internally to GNDD and should ideally be connected to the
ground of the video DAC IC.
S TA N D A R D P A R T O R D E R IN G IN F O R M A TIO N
Package
Ordering Part Num ber
Part Marking
Pins
Style
24
QSOP
PACVGA200Q
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved.
3/00
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
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