U404 [CALOGIC]
Dual N-Channel JFET Switch; 双N沟道JFET开关
| 型号： | U404 |
| 厂家： | 
CALOGIC, LLC |
| 描述： | Dual N-Channel JFET Switch |
| 文件： | 总2页 (文件大小：30K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual N-Channel JFET Switch
CORPORATION
U401 – U406
FEATURES
ABSOLUTE MAXIMUM RATINGS
(TA = 25oC unless otherwise specified)
Minimum System Error and Calibration
Low Drift With Temperature
Operates From Low Power Supply Voltages
High Output Impedance
•
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . . 50V
Gate Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Storage Temperature Range . . . . . . . . . . . . . -65oC to +200oC
Operating Temperature Range . . . . . . . . . . . -55oC to +150oC
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC
•
•
•
PIN CONFIGURATION
One Side
300mW
Both Sides
500mW
Power Dissipation (TA = 85oC)
Derate above 25oC
2.6mW/oC
5mW/oC
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TO-71
ORDERING INFORMATION
Part
Package
Temperature Range
U401-6
XU401-6
Hermetic TO-71
Sorted Chips in Carriers
-55oC to +150oC
-55oC to +150oC
D2
S2
G2
S1
G1
D1
CJ2
U401 – U406
CORPORATION
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)
U401
U402
U403
U404
U405
U406
SYMBOL
PARAMETER
UNITS
TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Gate-Source
Breakdown Voltage
BVGSS
-50
-.5
-50
-.5
-50
-.5
-50
-.5
-50
-.5
-50
-.5
V
VDS = 0, IG = -1µA
Gate Reverse Current
(Note 2)
IGSS
-25
-2.5
-2.3
10.0
-25
-2.5
-2.3
10.0
-25
-2.5
-2.3
10.0
-25
-2.5
-2.3
10.0
-25
-2.5
-2.3
10.0
-25
-2.5
-2.3
10.0
pA
VDS = 0, VGS = -30V
VDS = 15V, ID = 1nA
VDG = 15V, ID = 200µA
Gate-Source Cutoff
Voltage
VGS(off)
VGS(on)
IDSS
V
Gate-Source Voltage
(on)
Saturation Drain
Current (Note 3)
0.5
0.5
0.5
0.5
0.5
0.5
mA VDS = 10V, VGS = 0
-15
-10
-15
-10
-15
-10
-15
-10
-15
-10
-15
-10
pA
nA
VDG = 15V, ID = 200µA
A = 125oC
DS = 0, VGS = 0,
G = ±1µA
Operating Gate
Current (Note 2)
IG
T
V
I
Gate-Gate
Breakdown Voltage
BVG1-G2
V
±50
±50
±50
±50
±50
±50
Common-Source
Forward
Transconductance
(Note 3)
gfs
2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000
VDS = 10V,
VGS = 0
f = 1kHz
f = 1kHz
f = 1MHz
Common-Source
Output Conductance
gos
20
20
20
20
20
20
µS
Common-Source
Forward
gfs
1000 2000 1000 2000 1000 2000 1000 2000 1000 2000 1000 2000
Transconductance
VDG = 15V,
ID = 200µA
Common-Source
Output Conductance
gos
2.0
8.0
2.0
8.0
2.0
8.0
2.0
8.0
2.0
8.0
2.0
8.0
Common-Source
Input Capacitance
(Note 6)
Ciss
pF
Common-Source
Reverse Transfer
Capacitance (Note 6)
Crss
3.0
20
3.0
20
3.0
20
3.0
20
3.0
20
3.0
20
Equivalent
Short-Circuit Input
Noise Voltage
nV
√Hz
VDS = 15V, f = 10Hz
VGS = 0 (Note 6)
en
V
DG = 10 to 20V,
Common-Mode
Rejection Ratio
CMRR
95
95
95
95
90
dB
ID = 200µA (Note 5, 6)
Differential
Gate-Source Voltage
| VGS1 −VGS2
|
5
10
10
10
25
15
25
20
40
40
80
mV
VDG = 10V, ID = 200µA
Gate-Source Voltage
Differential Drift (Note
4)
T
A = -55oC
| ∆VGS1 −VGS2
∆T
|
V
DG = 10V,
10
TB = +25oC
µV/oC
ID = 200µA
TC = +125oC
NOTES: 1. Per transistor.
2. Approximately doubles for every 10oC increase in TA.
3. Pulse test duration = 300µs; duty cycle ≤3%.
4. Measured at end points TA, TB, TC.
∆VDD
5. CMRR = 20 log10
, ∆VDD = 10V.
∆ | VGS −VGS
|
2
1
6. For design reference only, not 100% tested.
相关型号：
U404-E3
Small Signal Field-Effect Transistor, N-Channel, Junction FETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
U404NL
Small Signal Field-Effect Transistor, N-Channel, Junction FETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
U404_TO-71
Low Noise, Low Drift, Monolithic Dual N-Channel JFETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROSS
U404_TO-78
Low Noise, Low Drift, Monolithic Dual N-Channel JFETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROSS
U405
N-CHANNEL JFETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INTERSIL
U405
Dual N-Channel JFET SwitchWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
CALOGIC
U405
LOW NOISE LOW DRIFT MONOLITHIC DUAL N CHANNEL JFETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
Linear System
U405
Low Noise, Low Drift, Monolithic Dual N-Channel JFETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROSS
U4050B
Speech Circuit with Line-Powered Loudspeaker AmplifierWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
U4050B-AFL
Speech Circuit with Line-Powered Loudspeaker AmplifierWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
U4050B-AFLG3
Speech Circuit with Line-Powered Loudspeaker AmplifierWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
U4050B-FL
Telecom IC, PDSO28,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明