U423 [CALOGIC]
N-Channel Dual JFET; N沟道JFET双
| 型号： | U423 |
| 厂家： | 
CALOGIC, LLC |
| 描述： | N-Channel Dual JFET |
| 文件： | 总2页 (文件大小：32K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N-Channel Dual JFET
CORPORATION
U421 – U426
FEATURES
DESCRIPTION
Ultra Low Input Bias Current . . . . . . . 250 Fempto Amps
Low Operating Current
Tight Matching Characteristics
The Calogic U421 Series are Dual N-Channel JFETs on a
monolithic structure designed specifically for very high input
impedance for differential amplification and impedance
matching. This series features ultra low input bias current
(250 fempto amps, U421) while offering high gain at low
operating currents and tight matching characteristics. These
devices are available in chip form for hybrid designs as well
as a hermetic TO-78 package.
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APPLICATIONS
Ultra Low Leakage FET Input Op Amps
Electrometer
Infrared Detectors
pH Meters
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ORDERING INFORMATION
Part
Package
Temperature Range
U421-U426
TO-78 Hermetic Package -55oC to +150oC
XU421-U426 Sorted Chips in Carriers -55oC to +150oC
PIN CONFIGURATION
TO-78
1 SOURCE 1
5
1
4
2 DRAIN 1
3 GATE 1
4 CASE/BODY
5 SOURCE 2
6 DRAIN 2
7 GATE 2
6
3
7
2
BOTTOM VIEW
G2
D2
S2
C
S1
G1
D1
CJ4
U421 – U426
CORPORATION
ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise noted)
Gate-to-Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40V
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -40V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Device Dissipation (Each Side), TA = 25oC
Total Device Dissipation, TA = 25oC
(Derate 6.0 mW/ oC to 150oC). . . . . . . . . . . . . 750 mW
Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC
(Derate 3.2 mW/ oC to 150oC). . . . . . . . . . . . . . 400mW
ELECTRICAL CHARACTERISTICS (25oC Unless otherwise noted)
U421-3
U424-6
SYMBOL
CHARACTERISTIC
UNIT
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
STATIC
BVGSS
Gate-Source Breakdown Voltage
Gate-Gate Breakdown Voltage
-60
IG = -1µA, VDS = 0
IG = -1µA, ID = 0, IS = 0
T = +25oC
-40
-60
-40
V
BVG1G2
±40
±40
1.0
1.0
3.0
3.0
pA
nA
V
GS = -20V,
DS = 0
IGSS
Gate Reverse Current (1)
Gate Operating Current (1)
T = +125oC
T = +25oC
T = +125oC
V
.25
0.5
VDG = 10V,
IG
pA
ID = 30µA
.250
-500
-2.0
-2.9
1800
VGS (off)
VGS
Gate-Source Cutoff Voltage
Gate-Source Voltage
VDS = 10V, ID = 1nA
VDG = 10V, ID = 30µA
VDS = 10V, VGS = 0
-0.4
60
-2.0 -0.4
-1.8
V
IDSS
Saturation Drain Current
1000
60
µA
DYNAMIC
gfs
Common-Source Forward Transconductance
Common-Source Output Conductance
Common-Source Input Capacitance
300
1500 300
1500
10
f = 1 kHz
gos
10
3.0
1.5
VDS = 10V,
VGS = 0
Ciss
3.0
1.5
350
3.0
70
f = 1MHz
f = 1kHz
pF
Crss
Common-Source Reverse Transfer Capacitance
Common-Source Forward Transconductance
Common-Source Output Conductance
gfs
120
350
3.0
70
120
gos
VDG = 10V,
f = 10Hz
f = 1kHz
f = 10 Hz
20
10
20
10
en
Equivalent Short Circuit Input
Noise Figure
nV/ Hz
dB
ID = 30µA
NF
1.0
1.0
R
G = 10 MΩ
U421,4
U422,5
U423,6
SYMBOL
CHARACTERISTIC
UNIT
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
MATCH
| VGS1-VGS2
|
|
Differential Gate-Source Voltage
VDG = 10V, ID = 30µA
VDG = 10V, ID = 30µA,
T
T
10
10
15
25
25
40
mV
V/ oC
dB
| VGS1-VGS2
Differential Gate-Source Voltage
Change with Temperature (2)
A = -55oC, TB = 25oC,
C = 125oC
∆T
CMRR
Common Mode Rejection Ratio (3)
ID = 30µA, VDG = 10 to 20 V
90
95
80 90
80
90
NOTES:
VDD
VGS1-VGS2
3. CMRR = 20log10
VDD = 10V.
1. Approximately doubles for every 10oC increase in TA.
[
]
2. Measured at endpoints TA, TB and TC.
4. Case lead not connected.
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