1024ZE-25TE13
更新时间：2024-10-29 16:47:44
品牌：CATALYST
描述：Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO8, MSOP-8
概述
规格参数
数据手册1024ZE-25TE13 概述
Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO8, MSOP-8 电源管理电路
1024ZE-25TE13 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Obsolete |
| 零件包装代码： | MSOP | 包装说明： | TSSOP, |
| 针数： | 8 | Reach Compliance Code： | unknown |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.68 | 可调阈值： | NO |
| 模拟集成电路 - 其他类型： | POWER SUPPLY SUPPORT CIRCUIT | JESD-30 代码： | R-PDSO-G8 |
| JESD-609代码： | e3 | 信道数量： | 1 |
| 功能数量： | 1 | 端子数量： | 8 |
| 最高工作温度： | 125 °C | 最低工作温度： | -40 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TSSOP |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| 峰值回流温度（摄氏度）： | 260 | 认证状态： | Not Qualified |
| 座面最大高度： | 1.1 mm | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 2.7 V | 标称供电电压 (Vsup)： | 3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | AUTOMOTIVE | 端子面层： | MATTE TIN |
| 端子形式： | GULL WING | 端子节距： | 0.65 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 3 mm | Base Number Matches： | 1 |
1024ZE-25TE13 数据手册
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PDF下载Preliminary Information
CAT1024, CAT1025
Supervisory Circuits with I2C Serial 2K CMOS EEPROM and Manual Reset
FEATURES
■ Built-in inadvertent write protection
— WP pin (CAT1025)
■ Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
■ Active high or low reset
■ 1,000,000 Program/Erase cycles
■ Manual reset input
■ 100 year data retention
— Valid reset guaranteed at VCC=1V
■ 400kHz I2C bus
■ 8-pin DIP, SOIC, TSSOP, TDFN (MSOP
(3x4.9mm) & 3x3mm foot prints) or MSOP
packages
■ 2.7V to 5.5V operation
■ Low power CMOS technology
■ 16-Byte page write buffer
■ Automotive, extended automotive and
industrial temperature ranges
DESCRIPTION
voltages support 5V, 3.3V and 3V systems. If power supply
voltages are out of tolerance reset signals become active,
preventing the system microcontroller, ASIC or peripherals
from operating. Reset signals become inactive typically 200
ms after the supply voltage exceeds the reset threshold
level. With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. In addition, the
RESET pin or a separate input, MR, can be used as an input
for push-button manual reset capability.
The CAT1024 and CAT1025 are complete memory and
supervisorysolutionsformicrocontroller-basedsystems.
A 2kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I2C bus.
The CAT1025 provides a precision VCC sense circuit
and two open drain outputs: one (RESET) drives high
and the other (RESET) drives low whenever VCC falls
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a VCC
sense circuit that prevents writes to memory whenever VCC
falls below the reset threshold or until VCC reaches the reset
threshold during power up.
The CAT1024 also provides a precision VCC sense
circuit, but has only a RESET output and does not have
a Write Protect input.
Available packages include an 8-pin DIP and a surface
mount8-pinSO,8-pinTSSOP,8-pinTDFNand8-pinMSOP
packages.TheTDFNpackagethicknessis0.8mmmaximum.
TDFN footprint options are 3x3mm or 3x4.9mm (MSOP pad
layout).
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4)
(Bottom View)
TDFN Package: 3mm x 4.9mm
0.8mm maximum height - (RD2)
PIN CONFIGURATION
V
MR
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
V
MR
CC
NC
MR
RESET
NC
V
1
2
3
4
8
7
6
5
CC
NC
CC
RESET
NC
NC
RESET
NC
CAT1024
CAT1024
CAT1024
SCL
SDA
SCL
SDA
SCL
SDA
V
SS
V
SS
V
SS
V
MR
8
7
6
5
V
MR
1
1
1
2
3
4
8
8
7
6
5
MR
V
CC
CC
CC
RESET
RESET
WP
SCL
SDA
2
3
4
RESET
RESET
WP
SCL
SDA
7
6
5
RESET 2
WP
CAT1025
CAT1025
CAT1025
3
4
SCL
SDA
RESET
V
V
SS
V
SS
SS
© 2003 by Catalyst Semiconductor, Inc.
Doc No. 3008, Rev. G
Characteristics subject to change without notice
CAT1024, CAT1025
Preliminary Information
Threshold Voltage Options
BLOCK DIAGRAM — CAT1024, CAT1025
Part Dash Minimum Maximum
Number Threshold Threshold
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
D
OUT
-45
-42
4.50
4.25
4.75
4.50
ACK
V
CC
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
V
SS
-30
-28
-25
3.00
2.85
2.55
3.15
3.00
2.70
START/STOP
SDA
WP*
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
SLAVE
MR
ADDRESS
COMPARATORS
Vcc Monitor
*
RESET RESET
*CAT1025 Only
OPERATING TEMPERATURE RANGE
PIN FUNCTIONS
Industrial
Automotive
Extended
-40˚C to 85˚C
-40˚C to 105˚C
-40˚C to 125˚C
Pin Name
Function
NC
RESET
VSS
No Connect
Active Low Reset Input/Output
Ground
SDA
Serial Data/Address
Clock Input
SCL
RESET
Active High Reset Output (CAT1025 only)
VCC
WP
MR
Power Supply
Write Protect (CAT1025 only)
Manual Reset Input
Doc. No. 3008, Rev. G
2
Preliminary Information
PIN DESCRIPTION
CAT1024, CAT1025
RESET/RESET: RESET OUTPUTS
MR:
MANUAL RESET INPUT
(RESET CAT1025 Only)
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset condition.
Reset outputs are active while MR input is low and for
the reset timeout period after MR returns to high. The
input has an internal pull up resistor.
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
thepinthedevicewillinitiateandmaintainaresetcondition.
The RESET pin must be connected through a pull-down
resistor, and the RESET pin must be connected through a
pull-up resistor.
WP (CAT1025 Only): WRITE PROTECT INPUT
When tied to VSS or left unconnected write operations
to the entire array are allowed. When tied to VCC, the
entire array is protected. This input has an internal pull
down resistor.
SDA: SERIAL DATA ADDRESS
Thebidirectionalserialdata/addresspinisusedtotransfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
SCL: SERIAL CLOCK
Serial clock input.
CAT10XX FAMILY OVERVIEW
Manual
Reset
Input Pin
Watchdog
Monitor
Pin
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET: Active
High and LOW
Device
Watchdog
EEPROM
CAT1021
SDA
2k
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
SDA
WDI
2k
2k
2k
2k
2k
2k
WDI
For Supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
Doc No. 3008, Rev. G
3
CAT1024, CAT1025
Preliminary Information
Stresses above those listed under “Absolute Maximum Ratings” may
causepermanentdamagetothedevice. Thesearestressratingsonly,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on any Pin with
Note:
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
(1) The minimum DC input voltage is –0.5V. During transitions,
inputs may undershoot to –2.0V for periods of less than 20 ns.
VCC with Respect to Ground ............... –2.0V to +7.0V
Maximum DC voltage on output pins is V +0.5V, which may
CC
Package Power Dissipation
overshoot to V +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than
one output shorted at a time.
CC
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.7V to +5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
VIN = GND to Vcc
VIN = GND to Vcc
Min
-2
Typ
Max
10
Units
µA
ILI
Input Leakage Current
Output Leakage Current
ILO
-10
10
µA
f
SCL = 400kHz
VCC = 5.5V
ICC1
ICC2
ISB
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
3
1
mA
mA
µA
f
SCL = 400kHz
VCC = 5.5V
Vcc = 5.5V,
40
VIN = GND or Vcc
3
VIL
Input Low Voltage
Input High Voltage
-0.5
0.3 x Vcc
Vcc + 0.5
V
V
3
VIH
0.7 x Vcc
Output Low Voltage
IOL = 3mA
VCC = 2.7V
VOL
VOH
0.4
V
V
(SDA, RESET)
Output High Voltage
(RESET)
IOH = -0.4mA
VCC = 2.7V
Vcc -
0.75
CAT102x-45
(VCC = 5V)
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
CAT102x-42
(VCC = 5V)
CAT102x-30
(VCC = 3.3V)
VTH
Reset Threshold
V
CAT102x-28
(VCC = 3.3V)
CAT102x-25
(VCC = 3V)
VRVALID
Reset Output Valid VCC Voltage
Reset Threshold Hysteresis
1.00
15
V
1
VRT
mV
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V + 1V.
CC
3.
V min and V max are reference values only and are not tested.
IL IH
Doc. No. 3008, Rev. G
4
Preliminary Information
CAPACITANCE
CAT1024, CAT1025
T = 25°C, f = 1.0 MHz, V
A
= 5V
CC
Symbol Test
Test Conditions
VOUT = 0V
Max
8
Units
(1)
COUT
Output Capacitance
Input Capacitance
pF
pF
(1)
CIN
VIN = 0V
6
A.C. CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle2
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
Input Filter Spike
Suppression (SDA, SCL)
tSP
100
ns
tLOW
tHIGH
Clock Low Period
Clock High Period
1.3
0.6
µs
µs
ns
ns
µs
1
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
300
300
1
tF
tHD;STA
tSU;STA
0.6
0.6
Start Condition Setup Time
(for a Repeated Start)
µs
tHD;DAT
tSU;DAT
tSU;STO
tAA
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
0
ns
ns
µs
ns
ns
100
0.6
900
tDH
50
Time the Bus must be Free Before a
New Transmission Can Start
1
tBUF
1.3
µs
3
tWC
Write Cycle Time (Byte or Page)
5
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
Doc No. 3008, Rev. G
5
CAT1024, CAT1025
Preliminary Information
RESET CIRCUIT A.C. CHARACTERISTICS
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPURST
tRPD
Reset Timeout
Note 2
Note 3
130
200
270
5
ms
µs
VTH to RESET output Delay
tGLITCH
MR Glitch
tMRW
VCC Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
Note 4, 5
Note 1
30
ns
ns
µs
100
Note 1
5
tMRD
MR Input to RESET Output Delay
Note 1
1
µs
POWER-UP TIMING5,6
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
270
270
ms
ms
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
3. Power-Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
4.
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. and t are the delays required from the time V is stable until the specified memory operation can be initiated.
V
Glitch Reference Voltage = V ; Based on characterization data
THmin
CC
t
PUR
PUW
CC
AC TEST CONDITIONS
Input pulse voltages
0.2VCC to 0.8VCC
10 ns
Input rise and fall times
Input reference voltages
Output reference voltages
0.3VCC, 0.7VCC
0.5VCC
Current Source: IOL = 3mA;
CL = 100pF
Output Load
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
(1)
VZAP
Volts
(1)(2)
ILTH
mA
Doc. No. 3008, Rev. G
6
Preliminary Information
CAT1024, CAT1025
DEVICE OPERATION
Reset Controller Description
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM are
aborted and no new communications are allowed. In this
conditionaninternalwritecycletothememorycannotbe
started, but an in progress internal non-volatile memory
write cycle can not be aborted. An internal write cycle
initiated before the Reset condition can be successfully
finishedifthereisenoughtime(5ms)beforeVCCreaches
the minimum value of 2V.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST
)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this point
the reset outputs will be pulled up or down by their
respective pull up/down resistors.
In addition, the CAT1025 includes a Write Protection Input
which when tied to VCC will disable any write operations
to the device.
During power-down, the RESET outputs will be active
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designedtoignorethefastnegativegoingVCC transient
pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
TheRESET pincanoperateasresetoutputandmanual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
When RESET I/O is driven to the active state, the 200
msectimerwillbegintotimetheresetinterval. Ifexternal
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
CAT1024/25 also have a separate manual reset input.
Driving the MR input low by connecting a pushbutton
(normally open) from MR pin to GND will generate a
reset condition. The input has a internal pull up resistor.
Reset remains asserted while MR is low and for the
Reset Timeout period after MR input has gone high.
Glitches shorter than 100 ns on MR input will not
generate a reset pulse. No external debouncing circuits
are required. Manual reset operation using MR input is
shown in Figure 2.
Hardware Data Protection
The CAT1024/25 family has been designed to solve
many of the data corruption issues that have long been
associatedwithserialEEPROMs. Datacorruptionoccurs
whenincorrectdataisstoredinamemorylocationwhich
is assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
Doc No. 3008, Rev. G
7
CAT1024, CAT1025
Preliminary Information
t
GLITCH
Figure 1. RESET Output Timing
V
TH
V
RVALID
t
RPD
t
V
t
PURST
CC
t
RPD
PURST
RESET
RESET
Figure 2. MR Operation and Timing
t
MRW
MR
t
t
MRD
PURST
RESET
RESET
Doc. No. 3008, Rev. G
8
Preliminary Information
CAT1024, CAT1025
EMBEDDED EEPROM OPERATION
SDA when SCL is HIGH. The CAT1024/25 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The CAT1024 and CAT1025 feature a 2kbit embedded
serial EEPROM that supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOPconditionsforbusaccess.BoththeMasterdevice
and Slave device can operate as either transmitter or
receiver, but the Master device controls which mode is
activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition.TheMastersendstheaddressoftheparticular
slave device it is requesting. The four most significant
bitsofthe8-bitslaveaddressareprogrammableinmetal
and the default is 1010.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
ReadorWriteoperationistobeperformed.Whenthisbit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT1024/25 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1024/25 then performs a Read or Write operation
depending on the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 3. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc No. 3008, Rev. G
9
CAT1024, CAT1025
Preliminary Information
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Byte Write
In the Byte Write mode, the Master device sends the
STARTconditionandtheslaveaddressinformation(with
theR/Wbitsettozero)totheSlavedevice.AftertheSlave
generates an acknowledge, the Master sends a 8-bit
address that is to be written into the address pointers of
thedevice. Afterreceivinganotheracknowledgefromthe
Slave, the Master device transmits the data to be written
into the addressed memory location. The CAT1024/25
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an
internalprogrammingcycletonon-volatilememory.While
the cycle is in progress, the device will not respond to any
request from the Master device.
The CAT1024/25 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress.Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
WhentheCAT1024/25beginsaREADmodeittransmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1024/25 will continue to transmit
data.IfnoacknowledgeissentbytheMaster,thedevice
terminates data transmission and waits for a STOP
condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7. Slave Address Bits
Default Configuration
1
0
1
0
0
0
0
R/W
Doc. No. 3008, Rev. G
10
Preliminary Information
CAT1024, CAT1025
Page Write
The CAT1024/25 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page
writeoperationisinitiatedinthesamemannerasthebyte
write operation, however instead of terminating after the
initialbyteistransmitted,theMasterisallowedtosendup
to 15 additional bytes. After each byte has been
transmitted, the CAT1024/25 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
IftheMastertransmitsmorethan16bytesbeforesending
theSTOPcondition, theaddresscounter‘wrapsaround,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1024/25 in a single write cycle.
Figure 8. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 9. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc No. 3008, Rev. G
11
CAT1024, CAT1025
Acknowledge Polling
Preliminary Information
memory array is protected and becomes read only. The
CAT1025 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issuedtoindicatetheendofthehost’swriteopration, the
CAT1024/25initiatestheinternalwritecycle.ACKpolling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation.Ifthedeviceisstillbusywiththewriteoperation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
Read Operations
The READ operation for the CAT1024/25 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
WRITE PROTECTION
The Write Protection feature (CAT1025 only) allows the
user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 3008, Rev. G
12
Preliminary Information
CAT1024, CAT1025
Immediate/Current Address Read
acknowledge but will generate a STOP condition.
The CAT1024 and CAT1025 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=255. The counter will wrap around to Zero and
continue to clock out valid data for the 2K devices. After
the CAT1024 and CAT1025 receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge, but
will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1024 and CAT1025 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data.TheCAT1024andCAT1025willcontinuetooutput
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1024 and
CAT1025issentsequentiallywiththedatafromaddress
N followed by data from address N+1. The READ
operationaddresscounterincrementsalloftheCAT1024
and CAT1025 address bits so that the entire memory
array can be read during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After the CAT1024 and CAT1025
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1024 and CAT1025 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc No. 3008, Rev. G
13
CAT1024, CAT1025
Preliminary Information
PACKAGE OUTLINES
TDFN 3X4.9 PACKAGE (RD2)
A
5
8
8
5
B
2.00 + 0.15
0.15
0.20
0.60 + 0.10 (8X)
PIN 1 ID
2x
d
0.15 c
1
4
3.00 + 0.10
(S)
4
1
2x
d
0.15 c
0.30 + 0.05 (8X)
8x
0.65 TYP. (6x)
PIN 1 INDEX AREA
1.95 REF. (2x)
j
0.10m C A B
0.75 + 0.05
f 0.10 c
0.20 REF.
8x
d 0.08 c
C
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
COPLANARITY SHALL NOT EXCEED 0.08mm.
3. WARPAGE SHALL NOT EXCEED 0.10mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL
CHARACTERISTIC(S).
5. REFER TO JEDEC MO-229, FOOTPRINTS ARE COMPATIBLE TO 8 MSOP.
0.0-0.05
Doc. No. 3008, Rev. G
14
Preliminary Information
CAT1024, CAT1025
TDFN 3X3 PACKAGE (RD4)
0.75 + 0.05
A
8
5
B
2X
2X
0.15
C
1
4
3.00 + 0.10
(S)
0.0 - 0.05
0.15
C
PIN 1 INDEX AREA
5
8
0.75 + 0.05
2.30 + 0.10
C0.35
C
0.25 min.
PIN 1 ID
0.30 + 0.10 (8x)
1
0.30 + 0.07 (8x)
0.65 TYP. (6x)
1.95 REF. (2x)
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY SHALL NOT EXCEED 0.08 mm.
3. WARPAGE SHALL NOT EXCEED 0.10 mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S)
5. REFER JEDEC MO-229 / WEEC
Doc No. 3008, Rev. G
15
CAT1024, CAT1025
Preliminary Information
Ordering Information
Prefix
Device #
1024
Suffix
-30
CAT
S
I
TE13
Optional
Company ID
Temperature Range
Tape & Reel
TE13: 2000/Reel
Product
Number
1024: 2K
I = Industrial (-40˚C to 85˚C)
A = Automotive (-40˚C to +105˚C)
E = Extended Automotive
1025: 2K
(-40˚C to +125˚C)
ResetThreshold
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
Package
P: PDIP
S: SOIC
R: MSOP
U: TSSOP
RD2: 8-pad TDFN
(3x4.9mm, MSOP Footprint)
RD4: 8-pad TDFN (3x3mm)
Note:
2
(1) The device used in the above example is a CAT1024SI-30TE13 (Supervisory circuit with I C serial 2k CMOS EEPROM, SOIC, Industrial
Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).
Doc. No. 3008, Rev. G
16
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION and SPECIFICALLY DISCLAIMS ANY and ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 3008
Revison:
Issue date:
Type:
G
4/8/03
Preliminary
www.catalyst-semiconductor.com
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