1026LE-28TE13
更新时间:2024-09-18 17:24:38
品牌:CATALYST
描述:Power Supply Support Circuit, Adjustable, 2 Channel, CMOS, PDIP8, PLASTIC, DIP-8
1026LE-28TE13 概述
Power Supply Support Circuit, Adjustable, 2 Channel, CMOS, PDIP8, PLASTIC, DIP-8 电源管理电路
1026LE-28TE13 规格参数
是否Rohs认证: | 符合 | 生命周期: | Obsolete |
零件包装代码: | DIP | 包装说明: | DIP, |
针数: | 8 | Reach Compliance Code: | unknown |
ECCN代码: | EAR99 | HTS代码: | 8542.39.00.01 |
风险等级: | 5.68 | 可调阈值: | YES |
模拟集成电路 - 其他类型: | POWER SUPPLY SUPPORT CIRCUIT | JESD-30 代码: | R-PDIP-T8 |
JESD-609代码: | e3 | 长度: | 13.87 mm |
信道数量: | 2 | 功能数量: | 1 |
端子数量: | 8 | 最高工作温度: | 125 °C |
最低工作温度: | -40 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | DIP | 封装形状: | RECTANGULAR |
封装形式: | IN-LINE | 峰值回流温度(摄氏度): | 260 |
认证状态: | Not Qualified | 座面最大高度: | 4.57 mm |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 2.7 V |
标称供电电压 (Vsup): | 3.3 V | 表面贴装: | NO |
技术: | CMOS | 温度等级: | AUTOMOTIVE |
端子面层: | MATTE TIN | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | 40 | 宽度: | 7.62 mm |
Base Number Matches: | 1 |
1026LE-28TE13 数据手册
通过下载1026LE-28TE13数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Preliminary Information
CAT1026, CAT1027
Dual Voltage Supervisory Circuits with I2C Serial 2K CMOS EEPROM
FEATURES
■ Precision VCC power supply voltage monitor
— 5V, 3.3V and 3V systems
■ 16-Byte page write buffer
■ Built-in inadvertent write protection
■ 1,000,000 Program/Erase cycles
■ Manual reset capability
— Five threshold voltage options
■ Additional voltage monitoring
— Externally adjustable down to 1.25V
■ 100 year data retention
■ Watchdog timer (CAT1027 only)
■ Active high or low reset
— Valid reset guaranteed to VCC=1V
■ 400kHz I2C bus
■ 8-pin DIP, SOIC, TSSOP, TDFN (MSOP
(3x4.9mm) & 3x3mm foot prints) or MSOP
packages
— TDFN max height is 0.8mm
■ Automotive, extended automotive and
■ 2.7V to 5.5V operation
industrial temperature ranges
■ Low power CMOS technology
DESCRIPTION
The CAT1026 and CAT1027 are complete memory and used as an input for push-button manual reset capability.
supervisorysolutionsformicrocontroller-basedsystems.
The CAT1026 and CAT1027 provide an auxiliary voltage
A 2kbit serial EEPROM memory and a system power
sensor input, VSENSE, which is used to monitor a second
supervisor with brown-out protection are integrated
system supply. The auxiliary high impedance comparator
together in low power CMOS technology. Memory
drives the open drain output, VLOW, whenever the sense
interface is via a 400kHz I2C bus.
voltage is below 1.25V threshold.
The CAT1026 and CAT1027 provide a precision VCC
TheCAT1027isdesignedwitha1.6secondwatchdogtimer
sense circuit with five reset threshold voltage options
circuit that resets a system to a known state if software or a
that support 5V, 3.3V and 3V systems. The power
hardware glitch halts or “hangs” the system. The CAT1027
supply monitor and reset circuit protects memory and
features a watchdog timer interrupt input, WDI.
systems controllers during power up/down and against
brownout conditions. If power supply voltages are out of
EEPROM memory features a 16-byte page. In addition,
tolerance reset signals become active preventing the
hardware data protection is provided by a VCC sense circuit
system microcontroller, ASIC, or peripherals from
that prevents writes to memory whenever VCC falls below
the reset threshold or until VCC reaches the reset threshold
operating.
during power up.
The CAT1026 features two open drain reset outputs:
one (RESET) drives high and the other (RESET) drives
low whenever VCC falls below the threshold. Reset
Available packages include 8-pin DIP and surface mount,
8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP
outputs become inactive typically 200 ms after the
packages. The TDFN package thickness is 0.8mm
supply voltage exceeds the reset threshold value. With
maximum. TDFN footprint options are 3x3mm or 3x4.9mm
both active high and low reset signals, interface to
(MSOP pad layout).
microcontrollers and other ICs is simple. CAT1027 has
onlyaRESET output. Inaddition, the RESET pincanbe
© 2003 by Catalyst Semiconductor, Inc.
Doc No. 3010, Rev. E
Characteristics subject to change without notice
CAT1026, CAT1027
BLOCK DIAGRAM
Preliminary Information
RESET Threshold Options
Part Dash Minimum Maximum
Number Threshold Threshold
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
D
OUT
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
ACK
V
V
CC
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
LOGIC
SDA
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
V
CC Monitor
HIGH VOLTAGE/
TIMING CONTROL
V
CC
STATE COUNTERS
SCL
SLAVE
ADDRESS
COMPARATORS
+
-
RESET
Controller
WDI
(CAT1027)
V
REF
Auxiliary Voltage Monitor
RESET
(CAT1026)
RESET
V
+
-
SENSE
V
LOW
V
REF
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4)
(Bottom View)
TDFN Package: 3mm x 4.9mm
0.8mm maximum height - (RD2)
PIN CONFIGURATION
8
7
6
5
1
2
3
4
V
V
V
V
LOW
1
2
3
4
1
2
3
4
V
V
8
7
6
5
8
7
6
5
CC
LOW
CC
LOW
CC
RESET
RESET
SCL
RESET
SCL
RESET
RESET
SCL
RESET
CAT1026
CAT1026
CAT1026
V
V
V
SENSE
SENSE
SENSE
SDA
V
SDA
V
V
SDA
SS
SS
SS
8
7
6
5
1
2
3
4
V
V
1
V
V
V
V
8
7
6
5
1
2
3
4
8
7
6
5
CC
LOW
CC
LOW
LOW
CC
RESET
WDI
SCL
SDA
2
3
4
WDI
SCL
SDA
RESET
WDI
SCL
SDA
RESET
CAT1027
CAT1027
CAT1027
V
V
V
SENSE
SENSE
SENSE
V
V
SS
V
SS
SS
Doc. No. 3010, Rev. E
2
Preliminary Information
PIN DESCRIPTION
CAT1026, CAT1027
RESET/RESET: RESET OUTPUTS
(RESET CAT1026 Only)
VSENSE: AUXILIARY VOLTAGE MONITOR INPUT
The VSENSE input is a second voltage monitor which
is compared against CAT1026 and CAT1027 internal
reference voltage of 1.25V typically. Whenever the
input voltage is lower than 1.25V, the open drain
VLOW output will be driven low. An external resistor
divider is used to set the voltage level to be sensed.
Connect VSENSE to VCC if unused.
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
thepinthedevicewillinitiateandmaintainaresetcondition.
The RESET pin must be connected through a pull-down
resistor, and the RESET pin must be connected through a
pull-up resistor.
VLOW: AUXILIARY VOLTAGE MONITOR OUTPUT
This open drain output goes low when VSENSE is less
than 1.25V and goes high when VSENSE exceeds the
reference voltage.
SDA: SERIAL DATA ADDRESS
Thebidirectionalserialdata/addresspinisusedtotransfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
WDI (CAT1027 Only): WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
SCL: SERIAL CLOCK
Serial clock input.
OPERATING TEMPERATURE RANGE
PIN FUNCTIONS
Industrial
Automotive
Extended
-40˚C to 85˚C
-40˚C to 105˚C
-40˚C to 125˚C
Pin Name
RESET
VSS
Function
Active Low Reset Input/Output
Ground
SDA
Serial Data/Address
SCL
Clock Input
RESET
VCC
Active High Reset Output (CAT1026 only)
Power Supply
VSENSE
VLOW
Auxiliary Voltage Monitor Input
Auxiliary Voltage Monitor Output
WatchdogTimerInterrupt(CAT1027only)
WDI
CAT10XX FAMILY OVERVIEW
Manual
Reset
Input Pin
Watchdog
Monitor
Pin
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET: Active
High and LOW
Device
Watchdog
EEPROM
CAT1021
SDA
2k
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
SDA
WDI
2k
2k
2k
2k
2k
2k
WDI
For Supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
Doc No. 3010, Rev. E
3
CAT1026, CAT1027
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stressesabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods may affect device
performance and reliability.
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to
V
CC with Respect to Ground ............... –2.0V to +7.0V
-2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V
CC
+0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a
CC
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
time.
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.7V to +5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
VIN = GND to Vcc
VIN = GND to Vcc
fSCL = 400kHz
Min
-2
Typ
Max
10
Units
µA
ILI
Input Leakage Current
Output Leakage Current
ILO
-10
10
µA
Power Supply Current
(Write)
ICC1
ICC2
3
mA
mA
V
CC = 5.5V
Power Supply Current
(Read)
fSCL = 400kHz
VCC = 5.5V
1
50
Vcc = 5.5V
CAT1026
ISB
Standby Current
µA
VIN = GND or Vcc CAT1027
60
3
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3 x Vcc
Vcc + 0.5
V
V
3
VIH
0.7 x Vcc
I
OL = 3mA
VOL
VOH
0.4
V
V
(SDA, RESET , VLOW
)
VCC = 2.7V
Output High Voltage
(RESET)
IOH = -0.4mA
VCC = 2.7V
Vcc -
0.75
CAT102x-45
(VCC = 5V)
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
CAT102x-42
(VCC = 5V)
Reset Threshold
(VCC Monitor)
CAT102x-30
(VCC = 3.3V)
VTH
V
CAT102x-28
(VCC = 3.3V)
CAT102x-25
(VCC = 3V)
Reset Output Valid VCC
Voltage
VRVALID
1.00
15
V
mV
V
1
VRT
Reset Threshold Hysteresis
Auxiliary Voltage Monitor
Threshold
VREF
1.2
1.25
1.3
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V + 1V.
CC
3.
V min and V max are reference values only and are not tested.
IL IH
Doc. No. 3010, Rev. E
4
Preliminary Information
CAPACITANCE
CAT1026, CAT1027
T = 25°C, f = 1.0 MHz, V
A
= 5V
CC
Symbol Test
Test Conditions
VOUT = 0V
Max
8
Units
(1)
COUT
Output Capacitance
Input Capacitance
pF
pF
(1)
CIN
VIN = 0V
6
A.C. CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle2
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
Input Filter Spike
Suppression (SDA, SCL)
tSP
100
ns
tLOW
tHIGH
Clock Low Period
Clock High Period
1.3
0.6
µs
µs
ns
ns
µs
1
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
300
300
1
tF
tHD;STA
tSU;STA
0.6
0.6
Start Condition Setup Time
(for a Repeated Start)
µs
tHD;DAT
tSU;DAT
tSU;STO
tAA
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
0
ns
ns
µs
ns
ns
100
0.6
900
tDH
50
Time the Bus must be Free Before a
New Transmission Can Start
1
tBUF
1.3
µs
3
tWC
Write Cycle Time (Byte or Page)
5
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
Doc No. 3010, Rev. E
5
CAT1026, CAT1027
Preliminary Information
VOLTAGE MONITOR AND RESET CIRCUIT A.C. CHARACTERISTICS
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPURST
tRPD1
tGLITCH
tWD
Reset Timeout
Note 2
130
200
270
5
ms
µs
VTH to RESET output Delay
Note 3
VCC Glitch Reject Pulse Width
Watchdog Timeout
Note 4, 6
Note 1
30
2.1
5
ns
sec
µs
1.0
1.6
tRPD2
VSENSE to VLOW Delay
Note 5
POWER-UP TIMING6,7
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
270
270
ms
ms
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table.
CC
TH
3. Power-Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table.
CC
TH
4.
V
Glitch Reference Voltage = V
; Based on characterization data.
THmin
CC
5. 0<V
≤V , V
Output Reference Voltage and Load according to “AC Test Conditions” Table.
SENSE
CC
LOW
6. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
7. and t are the delays required from the time V is stable until the specified memory operation can be initiated.
t
PUR
PUW
CC
AC TEST CONDITIONS
Input pulse voltages
0.2VCC to 0.8VCC
10 ns
Input rise and fall times
Input reference voltages
Output reference voltages
0.3VCC, 0.7VCC
0.5VCC
Current Source: IOL = 3mA;
CL = 100pF
Output Load
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
(1)
VZAP
Volts
(1)(2)
ILTH
mA
Doc. No. 3010, Rev. E
6
Preliminary Information
CAT1026, CAT1027
DEVICE OPERATION
Reset Controller Description
The CAT1026 and CAT1027 precision RESET
controllers ensure correct system operation during
brownout and power up/down conditions. They are
configured with open drain RESET outputs.
Data Protection
TheCAT1026andCAT1027deviceshavebeendesigned
tosolvemanyofthedatacorruptionissuesthathavelong
been associated with serial EEPROMs. Data corruption
occurswhenincorrectdataisstoredinamemorylocation
which is assumed to hold correct data.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST
)
WheneverthedeviceisinaResetcondition,theembedded
EEPROM is disabled for all operations, including write
operations. If the Reset output(s) are active, in progress
communicationstotheEEPROMareabortedandnonew
communications are allowed. In this condition an internal
write cycle to the memory can not be started, but an in
progressinternalnon-volatilememorywritecyclecannot
be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum
value of 2V.
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this point
the reset outputs will be pulled up or down by their
respective pull up/down resistors.
During power-down, the RESET outputs will be active
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designedtoignorethefastnegativegoingVCC transient
pulses (glitches).
Reset output timing is shown in Figure 1.
In addition, to avoid data corruption due to the loss of
power supply voltage during the memory internal write
operation, the system controller should monitor the
unregulated DC power. Using the second voltage sensor,
Manual Reset Capability
TheRESET pincanoperateasresetoutputandmanual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
V
SENSE, to monitor an unregulated power supply, the
CAT1026 and CAT1027 signals an impending power
failure by setting VLOW low.
When RESET I/O is driven to the active state, the 200
msectimerwillbegintotimetheresetinterval. Ifexternal
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
Watchdog Timer
TheWatchdogTimerprovidesanindependentprotection
formicrocontrollers.Duringasystemfailure,theCAT1027
device will provide a reset signal after a time-out interval
of 1.6 seconds for a lack of activity. CAT1027 is designed
with the Watchdog timer feature on the WDI pin. If WDI
does not toggle within 1.6 second intervals, the reset
conditionwillbegeneratedonresetoutput.Thewatchdog
timer is cleared by any transition on monitored line.
Monitoring Two Voltages
The CAT1026 and CAT1027 feature a second voltage
sensor, VSENSE, which drives the open drain VLOW
output low whenever the input voltage is below 1.25V.
The auxiliary voltage monitor timing is shown in Figure
2.
As long as reset signal is asserted, the watchdog timer
will not count and will stay cleared.
By using an external resistor divider the sense circuitry
can be set to monitor a second supply in the system.
The circuit shown in Figure 3 provides an externally
adjustable threshold voltage, VTH_ADJ to monitor the
auxiliary voltage. The low leakage current at VSENSE
allows the use of large value resistors, to reduce the
system power consumption. The VLOW output can be
externally connected to the RESET output to generate
a reset condition when either of the supplies is invalid.
In other applications, VLOW signal can be used to
interrupt the system controller for an impending power
failure notification.
Doc No. 3010, Rev. E
7
CAT1026, CAT1027
Preliminary Information
t
GLITCH
Figure 1. RESET Output Timing
V
TH
V
RVALID
t
RPD1
t
V
t
PURST
CC
t
RPD1
PURST
RESET
RESET
Figure 2. Auxiliary Voltage Monitor Timing
V
REF
V
SENSE
t
t
t
t
RPD2
RPD2
RPD2
RPD2
V
LOW
Figure 3. Auxiliary Voltage Monitor
V
CC
V
AUX
CAT1026/27
Externally adjustable
threshold
Power Fail
Interrupt
V
LOW
R
1
V
TH-ADJ
V
SENSE
R
2
R
R
2
R
1 +
R
2
+
1
V
= V
×
= 1.25V ×
TH-ADJ
REF
R
R
2
2
Doc. No. 3010, Rev. E
8
Preliminary Information
CAT1026, CAT1027
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT1026 and CAT1027
monitortheSDAandSCLlinesandwillnotresponduntil
this condition is met.
EMBEDDED EEPROM OPERATION
The CAT1026 and CAT1027 feature a 2kbit embedded
serial EEPROM that supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOPconditionsforbusaccess.BoththeMasterdevice
and Slave device can operate as either transmitter or
receiver, but the Master device controls which mode is
activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition.TheMastersendstheaddressoftheparticular
slave device it is requesting. The four most significant
bitsofthe8-bitslaveaddressareprogrammableinmetal
and the default is 1010.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
ReadorWriteoperationistobeperformed.Whenthisbit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT1026 and CAT1027 monitor the
bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
address. The CAT1026 and CAT1027 then perform a
Read or Write operation depending on the R/W bit.
START Condition
The START Condition precedes all commands to the
Figure 4. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 5. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc No. 3010, Rev. E
9
CAT1026, CAT1027
Preliminary Information
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Byte Write
In the Byte Write mode, the Master device sends the
STARTconditionandtheslaveaddressinformation(with
theR/Wbitsettozero)totheSlavedevice.AftertheSlave
generates an acknowledge, the Master sends a 8-bit
address that is to be written into the address pointers of
thedevice. Afterreceivinganotheracknowledgefromthe
Slave, the Master device transmits the data to be written
into the addressed memory location. The CAT1026 and
CAT1027 acknowledge once more and the Master
generates the STOP condition. At this time, the device
begins an internal programming cycle to non-volatile
memory. Whilethecycleisinprogress, thedevicewillnot
respond to any request from the Master device.
The CAT1026 and CAT1027 respond with an
acknowledge after receiving a START condition and its
slave address. If the device has been selected along
with a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT1026 and CAT1027 begin a READ mode
it transmits 8 bits of data, releases the SDA line and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT1026 and CAT1027 will
continue to transmit data. If no acknowledge is sent by
theMaster,thedeviceterminatesdatatransmissionand
waits for a STOP condition.
Figure 6. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 7. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 8. Slave Address Bits
Default Configuration
1
0
1
0
0
0
0
R/W
Doc. No. 3010, Rev. E
10
Preliminary Information
CAT1026, CAT1027
Page Write
The CAT1026 and CAT1027 write up to 16 bytes of data
inasinglewritecycle, byusingthePageWriteoperation.
The page write operation is initiated in the same manner
asthebytewriteoperation,howeverinsteadofterminating
after the initial byte is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
beentransmitted,theCAT1026andCAT1027willrespond
with an acknowledge and internally increment the lower
order address bits by one. The high order bits remain
unchanged.
IftheMastertransmitsmorethan16bytesbeforesending
theSTOPcondition, theaddresscounter‘wrapsaround,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1026 and CAT1027 in a single write cycle.
Figure 9. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 10. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc No. 3010, Rev. E
11
CAT1026, CAT1027
Acknowledge Polling
Preliminary Information
Read Operations
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issuedtoindicatetheendofthehost’swriteopration, the
CAT1026 and CAT1027 initiate the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the device is still busy with the
write operation, no ACK will be returned. If a write
operation has completed, an ACK will be returned and
the host can then proceed with the next read or write
operation.
The READ operation for the CAT1026 and CAT1027 is
initiated in the same manner as the write operation with
one exception, the R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Figure 11. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 3010, Rev. E
12
Preliminary Information
CAT1026, CAT1027
Immediate/Current Address Read
Sequential Read
The CAT1026 and CAT1027 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=255. The counter will wrap around to Zero and
continue to clock out valid data for the 2K devices. After
the CAT1026 and CAT1027 receive a slave address
(with the R/W bit set t o one), an acknowledge is issued,
and the requested 8-bit byte is transmitted. The master
devicedoesnotsendanacknowledge, butwillgenerate
a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 send the
inital 8-bit byte requested, the Master responds with an
acknowledge which tells the device it requires more
data.TheCAT1026andCAT1027willcontinuetooutput
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1026 and
CAT1027issentsequentiallywiththedatafromaddress
N followed by data from address N+1. The READ
operationaddresscounterincrementsalloftheCAT1026
and CAT1027 address bits so that the entire memory
array can be read during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After the CAT1026 and CAT1027
acknowledge, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1026 and CAT1027 then
respond with an acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Figure 12. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 13. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc No. 3010, Rev. E
13
CAT1026, CAT1027
Preliminary Information
PACKAGE OUTLINES
TDFN 3X4.9 PACKAGE (RD2)
A
5
8
8
5
B
2.00 + 0.15
0.15
0.20
0.60 + 0.10 (8X)
PIN 1 ID
2x
d
0.15 c
1
4
3.00 + 0.10
(S)
4
1
2x
d
0.15 c
0.30 + 0.05 (8X)
8x
0.65 TYP. (6x)
PIN 1 INDEX AREA
1.95 REF. (2x)
j
0.10m C A B
0.75 + 0.05
f 0.10 c
0.20 REF.
8x
d 0.08 c
C
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
COPLANARITY SHALL NOT EXCEED 0.08mm.
3. WARPAGE SHALL NOT EXCEED 0.10mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL
CHARACTERISTIC(S).
5. REFER TO JEDEC MO-229, FOOTPRINTS ARE COMPATIBLE TO 8 MSOP.
0.0-0.05
Doc. No. 3010, Rev. E
14
Preliminary Information
CAT1026, CAT1027
TDFN 3X3 PACKAGE (RD4)
0.75 + 0.05
A
8
5
B
2X
2X
0.15
C
1
4
3.00 + 0.10
(S)
0.0 - 0.05
0.15
C
PIN 1 INDEX AREA
5
8
0.75 + 0.05
2.30 + 0.10
C0.35
C
0.25 min.
PIN 1 ID
0.30 + 0.10 (8x)
1
0.30 + 0.07 (8x)
0.65 TYP. (6x)
1.95 REF. (2x)
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY SHALL NOT EXCEED 0.08 mm.
3. WARPAGE SHALL NOT EXCEED 0.10 mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S)
5. REFER JEDEC MO-229 / WEEC
Doc No. 3010, Rev. E
15
CAT1026, CAT1027
Preliminary Information
Ordering Information
Prefix
Device #
1026
Suffix
-30
CAT
S
I
TE13
Optional
Company ID
Temperature Range
Tape & Reel
TE13: 2000/Reel
Product
Number
1026: 2K
I = Industrial (-40˚C to 85˚C)
A = Automotive (-40˚C to +105˚C)
E = Extended Automotive
1027: 2K
(-40˚C to +125˚C)
ResetThreshold
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
Package
P: PDIP
S: SOIC
R: MSOP
U: TSSOP
RD2: 8-pad TDFN
(3x4.9mm, MSOP Footprint)
RD4: 8-pad TDFN (3x3mm)
Note:
2
(1) The device used in the above example is a CAT1026SI-30TE13 (Supervisory circuit with I C serial 2k CMOS EEPROM, SOIC, Industrial
Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).
Doc. No. 3010, Rev. E
16
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 3010
Revison:
Issue date:
Type:
E
4/11/03
Preliminary
www.catalyst-semiconductor.com
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