24C01BR-TE13 [CATALYST]
EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8;
| 型号： | 24C01BR-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总7页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C01B
1K-Bit Serial EEPROM
FEATURES
I 1,000,000 Program/Erase Cycles
I 100 Year Data Retention
I 2-Wire Serial Interface
I 1.8 to 6.0Volt Operation
I 8-pin DIP, 8-pin SOIC, 8-pin TSSOP or 8-pin MSOP
I Low Power CMOS Technology
I 4-Byte Page Write Buffer
I Commercial, Industrial and Automotive
Temperature Ranges
I Self-Timed Write Cycle with Auto-Clear
DESCRIPTION
4-byte page write buffer. The device operates via a 2-
wire serial interface and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 8-pin MSOP.
The CAT24C01B is a 1K-bit Serial CMOS EEPROM
internallyorganizedas128wordsof8bitseach.Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT24C01B features a
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (J)
DIP Package (P)
EXTERNAL LOAD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
NC
NC
NC
SENSE AMPS
SHIFT REGISTERS
CC
NC
NC
NC
V
CC
TEST
D
OUT
TEST
ACK
SCL
SCL
V
V
CC
V
SDA
V
SS
SS
SDA
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SS
5020 FHD F01
START/STOP
SDA
LOGIC
MSOP Package (R)
TSSOP Package (U)
1
2
3
4
8
7
6
5
V
1
8
7
6
5
NC
NC
NC
CC
NC
NC
NC
V
CC
TEST
XDEC
EEPROM
TEST
SCL
2
3
4
CONTROL
LOGIC
SCL
V
SDA
V
SS
SS
SDA
DATA IN STORAGE
PIN FUNCTIONS
Pin Name
Function
No Connect
HIGH VOLTAGE/
TIMING CONTROL
NC
SDA
SCL
VCC
VSS
Serial Data/Address
Serial Clock
SCL
STATE COUNTERS
+1.8V to +6.0V Power Supply
Ground
TEST
Test Input (GND, VCC or
Floating)
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25085-00 7/99 S-1
1
CAT24C01B
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
= +1.8V to +6.0V, unless otherwise specified.
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
mA
µA
µA
µA
V
Test Conditions
fSCL = 100 KHz
ICC
Power Supply Current
3
(5)
ISB
Standby Current (VCC = 5.0V)
Input Leakage Current
0
10
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
ILI
ILO
Output Leakage Current
Input Low Voltage
10
VIL
–1
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Voltage
VCC x 0.7
V
VOL1
VOL2
Output Low Voltage (VCC = 3.0V)
Output Low Voltage (VCC = 1.8V)
V
IOL = 3 mA
0.5
V
IOL = 1.5 mA
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
Units
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
8
6
pF
pF
(3)
CIN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby Current (I ) = 0µA (<900nA).
SB
Doc. No. 25085-00 7/99 S-1
2
CAT24C01B
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, C =1TTL Gate and 100pF (unless otherwise specified).
L
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
4.5V-5.5V
Min.
Max.
Min.
Max.
Units
kHz
ns
FSCL
TI(1)
Clock Frequency
100
100
400
100
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
0.6
1.2
0.6
0.6
µs
µs
µs
µs
4.7
4
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
250
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4.7
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
tWR
Write Cycle Time
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its input.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 25085-00 7/99 S-1
3
CAT24C01B
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The CAT24C01B bidirectional serial data/address pin is
usedtotransferdataintoandoutofthedevice. TheSDA
pin is an open drain output and can be wired with other
open drain or open collector outputs.
The CAT24C01B uses a 2-wire data transmission pro-
tocol. Theprotocoldefinesanydevicethatsendsdatato
thebustobeatransmitterandanydevicereceivingdata
tobeareceiver. DatatransferiscontrolledbytheMaster
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24C01B
operates as a Slave device. Both the Master and Slave
devicescanoperateaseithertransmitterorreceiver,but
the Master device controls which mode is activated.
2-WIRE BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
PIN DESCRIPTIONS
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
SCL: Serial Clock
The CAT24C01B serial clock input pin is used to clock
alldatatransfersintooroutofthedevice. Thisisaninput
pin.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
AA
DH
SDA OUT
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
STOP BIT
Doc. No. 25085-00 7/99 S-1
4
CAT24C01B
START Condition
(withtheR/Wbitsettozero)totheSlavedevice.Afterthe
Slave generates an acknowledge, the Master sends the
byte address that is to be written into the address pointer
of the CAT24C01B. After receiving another acknowl-
edge from the Slave, the Master device transmits the
data byte to be written into the addressed memory
location. The CAT24C01B acknowledge once more and
the Master generates the STOP condition, at which time
the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C01B monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
Page Write
The CAT24C01B writes up to 4 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
tosendupto3additionalbytes.Aftereachbytehasbeen
transmitted the CAT24C01B will respond with an ac-
knowledge, and internally increment the low order ad-
dress bits by one. The high order bits remain un-
changed.
The CAT24C01B responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24C01B is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this acknowl-
edge, the CAT24C01B will continue to transmit data. If
no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
IftheMastertransmitsmorethan4bytespriortosending
theSTOPcondition,theaddresscounter‘wrapsaround,’
and previously transmitted data will be overwritten.
Once all 4 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C01B in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
Doc. No. 25085-00 7/99 S-1
5
CAT24C01B
Acknowledge Polling
ingwithanacknowledgeandbyissuingastopcondition.
Refer to Figure 7 for the start word address, read bit,
acknowledge and data transfer sequence.
The disabling of the inputs can be used to take advan-
tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C01B initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the byte
address for a write operation. If the CAT24C01B is still
busy with the write operation, no ACK will be returned.
IftheCAT24C01Bhascompletedthewriteoperation,an
ACK will be returned and the host can then proceed with
the next read or write operation.
Sequential Read
The Sequential READ operation can be initiated after
the 24C01B sends the initial 8-bit byte requested, the
Master will respond with an acknowledge which tells the
device it requires more data. The CAT24C01B will
continue to output an 8-bit byte for each acknowledge
sent by the Master. The operation is terminated when
the Master fails to respond with an acknowledge, thus
sending the STOP condition.
READ OPERATIONS
The data being transmitted from the CAT24C01B is
outputsequentiallywithdatafromaddressNfollowedby
data from address N+1. The READ operation address
counter increments all of the CAT24C01B address bits
so that the entire memory array can be read during one
operation. If more than bytes are read out, the counter
will “wrap around” and continue to clock out data bytes.
The READ operation for the CAT24C01B is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Two different
READ operations are possible: Byte READ and Se-
quential READ.
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, themastermusteitherissureastopcondition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Byte Read
To initiate a read operation, the master sends a start
condition followed by a seven bit word address and a
read bit. The CAT24C01B responds with an acknowl-
edge and then transmits the eight bits of data. The read
operation is terminated by the master; by not respond-
Figure5. Byte Write Timing
S
T
S
T
O
P
A
R
T
WORD
ADDRESS(n)
BUS ACTIVITY:
SDA LINE
P
S
A
C
K
L R
M
S
B
A
C
K
BUS ACTIVITY:
DATA n
S /
BW
Figure 6. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
WORD
ADDRESS(n)
DATA n
DATA n+3
DATA n+1
SDA LINE
P
S
A
C
K
L R
S /
BW
M
S
B
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
Doc. No. 25085-00 7/99 S-1
6
CAT24C01B
Figure 7. Byte Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
WORD
ADDRESS(n)
DATA n
MASTER
SDA LINE
P
S
A
C
K
M
S
B
L R
S /
BW
A
C
K
BUS ACTIVITY
CAT24C01B
Figure 8. Sequential Read Timing
S
T
O
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
MASTER
ADDRESS
SDA LINE
P
A
C
K
R
/
W
BUS ACTIVITY
CAT24C01B
DATA n
DATA n+x
DATA n+1
DATA n+2
ORDERING INFORMATION
Prefix
Device #
24C01B
Suffix
CAT
J
I
-1.8
TE13
Temperature Range
Product Number
24C01B: 1K
Tape & Reel
TE13: 2000/Reel
Optional
Company ID
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
* -40˚ to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 24C01BJI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Doc. No. 25085-00 7/99 S-1
7
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