CAT1022LI-45TE13
更新时间:2024-09-18 01:54:08
品牌:CATALYST
描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
CAT1022LI-45TE13 概述
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer 监控电路,带有I2C串行2K位CMOS EEPROM ,手动复位及看门狗定时器 电源管理电路
CAT1022LI-45TE13 规格参数
是否Rohs认证: | 符合 | 生命周期: | Transferred |
零件包装代码: | DIP | 包装说明: | DIP, |
针数: | 8 | Reach Compliance Code: | unknown |
ECCN代码: | EAR99 | HTS代码: | 8542.39.00.01 |
风险等级: | 5.25 | 可调阈值: | NO |
模拟集成电路 - 其他类型: | POWER SUPPLY MANAGEMENT CIRCUIT | JESD-30 代码: | R-PDIP-T8 |
JESD-609代码: | e3 | 长度: | 9.59 mm |
信道数量: | 1 | 功能数量: | 1 |
端子数量: | 8 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | DIP | 封装形状: | RECTANGULAR |
封装形式: | IN-LINE | 峰值回流温度(摄氏度): | 260 |
认证状态: | Not Qualified | 座面最大高度: | 4.57 mm |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 2.7 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | NO |
技术: | CMOS | 温度等级: | INDUSTRIAL |
端子面层: | Matte Tin (Sn) | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | 40 | 宽度: | 7.62 mm |
Base Number Matches: | 1 |
CAT1022LI-45TE13 数据手册
通过下载CAT1022LI-45TE13数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载E
CAT1021, CAT1022, CAT1023
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset
and Watchdog Timer
TM
FEATURES
■ Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
■ Watchdog timer
■ Built-in inadvertent write protection
— WP pin (CAT1021)
■ 1,000,000 Program/Erase cycles
■ Manual reset input
■ Active high or low reset
— Valid reset guaranteed at VCC = 1 V
■ 400kHz I2C bus
■ 100 year data retention
■ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3 mm foot-print) packages
— TDFN max height is 0.8mm
■ 3.0V to 5.5V operation
■ Industrial and extended temperature ranges
■ Low power CMOS technology
■ 16-Byte page write buffer
DESCRIPTION
The CAT1021, CAT1022 and CAT1023 are complete The power supply monitor and reset circuit protect memory
memory and supervisory solutions for microcontroller- and system controllers during power up/down and against
based systems. A 2k-bit serial EEPROM memory and a brownout conditions. Five reset threshold voltages support
system power supervisor with brown-out protection are 5V, 3.3V and 3V systems. If power supply voltages are out
integrated together in low power CMOS technology. of tolerance reset signals become active, preventing the
Memory interface is via a 400kHz I2C bus.
systemmicrocontroller, ASICorperipheralsfromoperating.
Reset signals become inactive typically 200 ms after the
supply voltage exceeds the reset threshold level. With both
activehighandlowresetsignals,interfacetomicrocontrollers
and other ICs is simple. In addition, the RESET pin or a
separate input, MR, can be used as an input for push-button
manual reset capability.
The CAT1021 and CAT1023 provide a precision VCC
sense circuit and two open drain outputs: one (RESET)
drives high and the other (RESET) drives low whenever
VCC fallsbelowtheresetthresholdvoltage.TheCAT1022
has only a RESET output and does not have a Write
Protect input. The CAT1021 also has a Write Protect
input (WP). Write operations are disabled if WP is The on-chip, 2k-bit EEPROM memory features a 16-byte
connected to a logic high.
page. In addition, hardware data protection is provided by a
VCC sense circuit that prevents writes to memory whenever
VCC falls below the reset threshold or until VCC reaches the
reset threshold during power up.
Allsupervisorshavea1.6secondwatchdogtimercircuit
that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. For the
CAT1021 and CAT1022, the watchdog timer monitors Available packages include an 8-pin DIP, 8-pin SOIC, 8-pin
theSDAsignal.TheCAT1023hasaseparatewatchdog TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN package
timer interrupt input pin, WDI.
thickness is 0.8mm maximum. TDFN footprint options are
3x3mm.
© 2004 by Catalyst Semiconductor, Inc.
Doc No. 3009, Rev. K
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
Threshold Voltage Options
BLOCK DIAGRAM
Part Dash Minimum Maximum
Number Threshold Threshold
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
D
OUT
ACK
V
V
CC
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
SDA
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
WP
(CAT1021)
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
SLAVE
MR
ADDRESS
COMPARATORS
Vcc Monitor
WDI
(CAT1023)
RESET
(CAT1021/23)
RESET
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
TSSOP Package (U, Y)
MSOP Package (R, Z)
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4, ZD4)
V
MR
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
CC
MR
V
CC
RESET
SCL
RESET
WP
RESET
RESET
CAT1021
CAT1021
WP
SCL
SDA
V
SS
V
SDA
SS
V
MR
1
2
3
4
8
7
6
5
8
1
CC
MR
V
CC
NC
SCL
SDA
RESET
RESET 2
NC
7
6
5
CAT1022
CAT1023
CAT1022
NC
NC
3
4
SCL
SDA
V
SS
V
SS
V
MR
1
8
7
6
5
1
8
7
6
5
MR
V
CC
CC
2
3
4
WDI
SCL
SDA
RESET
RESET
RESET 2
WDI
SCL
SDA
CAT1023
3
4
RESET
V
V
SS
SS
Doc. No. 3009, Rev. K
2
CAT1021, CAT1022, CAT1023
MR:
MANUAL RESET INPUT
PIN DESCRIPTION
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset condition.
Reset outputs are active while MR input is low and for
the reset timeout period after MR returns to high. The
input has an internal pull up resistor.
RESET/RESET: RESET OUTPUTS
(RESET CAT1021/23 Only)
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
thepinthedevicewillinitiateandmaintainaresetcondition.
The RESET pin must be connected through a pull-down
resistor, and the RESET pin must be connected through a
pull-up resistor.
WP (CAT1021 Only): WRITE PROTECT INPUT
When WP input is tied to VSS or left unconnected write
operations to the entire array are allowed. When tied to
VCC, the entire array is protected. This input has an
internal pull down resistor.
SDA: SERIAL DATA ADDRESS
Thebidirectionalserialdata/addresspinisusedtotransfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
SCL: SERIAL CLOCK
Serial clock input.
OPERATING TEMPERATURE RANGE
PIN FUNCTIONS
Industrial
Extended
-40˚C to 85˚C
-40˚C to 125˚C
Pin Name
Function
NC
RESET
VSS
No Connect
Active Low Reset Input/Output
Ground
SDA
SCL
Serial Data/Address
Clock Input
RESET
VCC
Active High Reset Output (CAT1021/23)
Power Supply
WP
Write Protect (CAT1021 only)
Manual Reset Input
MR
WDI
Watchdog Timer Interrupt (CAT1023)
CAT102X FAMILY OVERVIEW
Manual
Reset
Input Pin
Watchdog
Monitor
Pin
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET: Active
High and LOW
Device
Watchdog
EEPROM
CAT1021
SDA
2k
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
SDA
WDI
2k
2k
2k
2k
2k
2k
WDI
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
Doc No. 3009, Rev. K
3
CAT1021, CAT1022, CAT1023
Stresses above those listed under “Absolute Maximum Ratings” may
causepermanentdamagetothedevice. Thesearestressratingsonly,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on any Pin with
Note:
Respect to Ground(1) ........... –2.0 V to VCC + 2.0 V
(1) The minimum DC input voltage is –0.5V. During transitions,
inputs may undershoot to
VCC with Respect to Ground ................ –2.0V to 7.0 V
–2.0V for periods of less than 20 ns. Maximum DC voltage on
output pins is V +0.5V, which may overshoot to V +2.0V
for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than
one output shorted at a time.
CC
CC
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
DC OPERATING CHARACTERISTICS
V
CC
= 3.0V to 5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
VIN = GND to Vcc
VIN = GND to Vcc
Min
-2
Typ
Max
10
Units
µA
ILI
Input Leakage Current
Output Leakage Current
ILO
-10
10
µA
fSCL = 400 kHz
VCC = 5.5V
ICC1
ICC2
ISB
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
3
1
mA
mA
µA
fSCL = 400 kHz
VCC = 5.5 V
Vcc = 5.5 V,
VIN = GND or Vcc
60
(1)
VIL
Input Low Voltage
Input High Voltage
-0.5
0.3 x Vcc
Vcc + 0.5
V
V
(1)
VIH
0.7 x Vcc
Output Low Voltage
IOL = 3 mA
VCC = 2.7 V
VOL
VOH
0.4
V
V
(SDA, RESET)
Output High Voltage
(RESET)
IOH = -0.4 mA
VCC = 2.7 V
Vcc -
0.75
CAT102x-45
(VCC = 5.0 V)
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
CAT102x-42
(VCC = 5.0 V)
CAT102x-30
(VCC = 3.3 V)
VTH
Reset Threshold
V
CAT102x-28
(VCC = 3.3 V)
CAT102x-25
(VCC = 3.0 V)
VRVALID
Reset Output Valid VCC Voltage
Reset Threshold Hysteresis
1.00
15
V
(2)
VRT
mV
Notes:
1.
V
min and V max are reference values only and are not tested.
IH
IL
2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. 3009, Rev. K
4
CAT1021, CAT1022, CAT1023
CAPACITANCE
T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol Test
Test Conditions
VOUT = 0V
Max
Units
pF
(1)
COUT
Output Capacitance
Input Capacitance
8
6
(1)
CIN
VIN = 0V
pF
AC CHARACTERISTICS
VCC = 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
Input Filter Spike
Suppression (SDA, SCL)
tSP
100
ns
tLOW
tHIGH
Clock Low Period
Clock High Period
1.3
0.6
µs
µs
ns
ns
µs
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
300
300
(1)
tF
tHD;STA
tSU;STA
0.6
0.6
Start Condition Setup Time
(for a Repeated Start)
µs
tHD;DAT
tSU;DAT
tSU;STO
tAA
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
0
ns
ns
µs
ns
ns
100
0.6
900
tDH
50
Time the Bus must be Free Before a
New Transmission Can Start
(1)
tBUF
1.3
µs
(3)
tWC
Write Cycle Time (Byte or Page)
5
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
Doc No. 3009, Rev. K
5
CAT1021, CAT1022, CAT1023
RESET CIRCUIT AC CHARACTERISTICS
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPURST
tRPD
Reset Timeout
Note 2
Note 3
130
200
270
5
ms
µs
VTH to RESET Output Delay
tGLITCH
MR Glitch
tMRW
VCC Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
Note 4, 5
Note 1
Note 1
Note 1
30
ns
ns
µs
µs
100
5
tMRD
MR Input to RESET Output Delay
1
tWD
Watchdog Timeout
Note 1
1.0
1.6
2.3
sec
POWER-UP TIMING5,6
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
270
270
ms
ms
AC TEST CONDITIONS
Parameter
Test Conditions
0.2 VCC to 0.8 VCC
10 ns
Input Pulse Voltages
Input Rise and Fall times
Input Reference Voltages
Output Reference Voltages
0.3 VCC , 0.7 VCC
0.5 VCC
Current Source: IOL = 3 mA;
CL = 100 pF
Output Load
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
(5)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
Cycles/Byte
Years
(5)
TDR
Data Retention
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
(5)
VZAP
Volts
(5)(7)
ILTH
mA
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
3. Power-Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
4.
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. and t are the delays required from the time V is stable until the specified memory operation can be initiated.
V
Glitch Reference Voltage = V ; Based on characterization data
THmin
CC
t
PUR
PUW
CC
7. Latch-up protection is provided for stresses up to 100 mA on input and output pins from -1 V to V + 1 V.
CC
Doc. No. 3009, Rev. K
6
CAT1021, CAT1022, CAT1023
DEVICE OPERATION
Reset Controller Description
TheCAT1021/22/23precisionRESETcontrollersensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM are
aborted and no new communications are allowed. In this
condition aninternal write cycleto thememory cannot be
started, but an in progress internal non-volatile memory
write cycle can not be aborted. An internal write cycle
initiated before the Reset condition can be successfully
finishedifthereisenoughtime(5ms)beforeVCCreaches
the minimum value of 2V.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST
)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this point
the reset outputs will be pulled up or down by their
respective pull up/down resistors.
In addition, the CAT1021 includes a Write Protection Input
which when tied to VCC will disable any write operations
to the device.
During power-down, the RESET outputs will be active
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designedtoignorethefastnegativegoingVCC transient
pulses (glitches).
Watchdog Timer
TheWatchdogTimerprovidesanindependentprotection
for microcontrollers. During a system failure, CAT1021/
22/23 devices will provide a reset signal after a time-out
intervalof1.6secondsforalackofactivity. TheCAT1023
is designed with the Watchdog timer feature on the WDI
pin. The CAT1021 and CAT1022 monitor the SDA line. If
WDI or SDA does not toggle within a 1.6 second interval,
theresetconditionwillbegeneratedontheresetoutputs.
The watchdog timer is cleared by any transition on a
monitored line.
Reset output timing is shown in Figure 1.
Manual Reset Operation
TheRESET pincanoperateasresetoutputandmanual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
When RESET I/O is driven to the active state, the 200
msectimerwillbegintotimetheresetinterval. Ifexternal
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
As long as reset signal is asserted, the watchdog timer
will not count and will stay cleared.
TheCAT1021/22/23alsohaveaseparatemanualreset
input. Driving the MR input low by connecting a
pushbutton (normally open) from MR pin to GND will
generatearesetcondition.Theinputhasaninternalpull
up resistor.
Reset remains asserted while MR is low and for the
Reset Timeout period after MR input has gone high.
Glitches shorter than 100 ns on MR input will not
generate a reset pulse. No external debouncing circuits
are required. Manual reset operation using MR input is
shown in Figure 2.
Hardware Data Protection
The CAT1021/22/23 supervisors have been designed
to solve many of the data corruption issues that have
long been associated with serial EEPROMs. Data
corruption occurs when incorrect data is stored in a
memory location which is assumed to hold correct data.
Whenever the device is in a Reset condition, the
Doc No. 3009, Rev. K
7
CAT1021, CAT1022, CAT1023
t
GLITCH
Figure 1. RESET Output Timing
V
TH
V
RVALID
t
RPD
t
V
t
PURST
CC
t
RPD
PURST
RESET
RESET
Figure 2. MR Operation and Timing
t
MRW
MR
t
t
MRD
PURST
RESET
RESET
Doc. No. 3009, Rev. K
8
CAT1021, CAT1022, CAT1023
SDA when SCL is HIGH. The CAT1021/22/23 monitor
the SDA and SCL lines and will not respond until this
condition is met.
EMBEDDED EEPROM OPERATION
The CAT1021/22/23 feature a 2kbit embedded serial
EEPROM that supports the I2C Bus data transmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. Both the Master device and
Slavedevicecanoperateaseithertransmitterorreceiver,
but the Master device controls which mode is activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition.TheMastersendstheaddressoftheparticular
slave device it is requesting. The four most significant
bitsofthe8-bitslaveaddressareprogrammableinmetal
and the default is 1010.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
ReadorWriteoperationistobeperformed.Whenthisbit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT1021/22/23 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1021/22/23 then perform a Read or Write operation
depending on the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 3. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc No. 3009, Rev. K
9
CAT1021, CAT1022, CAT1023
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Byte Write
In the Byte Write mode, the Master device sends the
STARTconditionandtheslaveaddressinformation(with
theR/Wbitsettozero)totheSlavedevice.AftertheSlave
generates an acknowledge, the Master sends a 8-bit
address that is to be written into the address pointers of
thedevice. Afterreceivinganotheracknowledgefromthe
Slave, the Master device transmits the data to be written
into the addressed memory location. The device
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an
internalprogrammingcycletonon-volatilememory.While
the cycle is in progress, the device will not respond to any
request from the Master device.
Alldevicesrespondwithanacknowledgeafterreceiving
a START condition and its slave address. If the device
has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-
bit byte.
When a device begins a READ mode it transmits 8 bits
of data, releases the SDA line and monitors the line for
anacknowledge.Onceitreceivesthisacknowledge,the
device will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data
transmission and waits for a STOP condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7. Slave Address Bits
Default Configuration
1
0
1
0
0
0
0
R/W
Doc. No. 3009, Rev. K
10
CAT1021, CAT1022, CAT1023
Page Write
The CAT1021/22/23 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, the CAT1021/22/23 will respond with
anacknowledgeandinternallyincrementthelowerorder
address bits by one. The high order bits remain
unchanged.
IftheMastertransmitsmorethan16bytesbeforesending
theSTOPcondition, theaddresscounter‘wrapsaround,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1021/22/23 in a single write cycle.
Figure 8. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 9. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc No. 3009, Rev. K
11
CAT1021, CAT1022, CAT1023
Acknowledge Polling
memory array is protected and becomes read only. The
CAT1021 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issuedtoindicatetheendofthehost’swriteopration, the
CAT1021/22/23 initiates the internal write cycle. ACK
pollingcanbeinitiatedimmediately.Thisinvolvesissuing
the start condition followed by the slave address for a
write operation. If the device is still busy with the write
operation, no ACK will be returned. If a write operation
hascompleted, anACKwillbereturnedandthehostcan
then proceed with the next read or write operation.
Read Operations
The READ operation for the CAT1021/22/23 is initiated
in the same manner as the write operation with one
exception, the R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1021 only) allows the
user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 3009, Rev. K
12
CAT1021, CAT1022, CAT1023
Immediate/Current Address Read
Sequential Read
The CAT1021/22/23 address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N + 1. For N = E = 255, the
counter will wrap around to zero and continue to clock
out valid data. After the CAT1021/22/23 receives its
slave address information (with the R/W bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1021/22/23 sends the inital 8-
bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data.TheCAT1021/22/23willcontinuetooutputan8-bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1021/22/23 is
sent sequentially with the data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT1021/22/23
addressbitssothattheentirememoryarraycanberead
during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishestoread.AftertheCAT1021/22/23acknowledges,
the Master device sends the START condition and the
slaveaddressagain,thistimewiththeR/Wbitsettoone.
TheCAT1021/22/23thenrespondswithitsacknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a
STOP condition.
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc No. 3009, Rev. K
13
CAT1021, CAT1022, CAT1023
PACKAGE OUTLINES
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
D
0.120 (3.05)
0.150 (3.81)
0.180 (4.57) MAX
0.015 (0.38)
—
0.110 (2.79)
0.150 (3.81)
0.100 (2.54)
0.310 (7.87)
0.380 (9.65)
BSC
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Dimension D
Min
0.355 (9.02)
Pkg
Max
8L
0.400 (10.16)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
Doc. No. 3009, Rev. K
14
CAT1021, CAT1022, CAT1023
8-LEAD 150 MIL WIDE SOIC (J, W)
0.1497 (3.80) 0.2284 (5.80)
0.1574 (4.00) 0.2440 (6.20)
D
0.0532 (1.35)
0.0688 (1.75)
0.050 (1.27) BSC
0.0040 (0.10)
0.0098 (0.25)
0.013 (0.33)
0.020 (0.51)
0.0099 (0.25)
X 45°
0.0196 (0.50)
0.0075 (0.19)
0.0098 (0.25)
0°–8°
0.016 (0.40)
0.050 (1.27)
Dimension D
Pkg
Min
Max
0.1968(5.00)
8L
0.1890(4.80)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc No. 3009, Rev. K
15
CAT1021, CAT1022, CAT1023
8-LEAD TSSOP (U, Y)
Doc. No. 3009, Rev. K
16
CAT1021, CAT1022, CAT1023
8 LEAD MSOP (R, Z)
0.38
0.28
0.0150
0.0110
0.1970
0.1890
5.00
4.80
S
0.0256 [0.65] BSC
3.10
2.90
0.1220
0.1142
0.0374
0.0295
0.95
0.75
0.0433 [1.10] MAX.
0.0059
0.0020
0.15
0.05
0.039 [0.10] MAX.
S
S
0.0150
0.0110
0.38
0.28
WITH PLATING
0.0091 0.23
0.0051 0.13
0.0050 [0.127]
BASE METAL
0.1220
0.1142
3.10
2.90
0.0276
0.0157
0.70
0.40
0˚ - 6˚
WITH PLATING
0.0118 [0.30] REF.
SECTION A - A
Notes:
(1) All dimensions are in mm Angles in degrees.
2
3
4
Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side.
Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side.
Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm.
(5) This part is compliant with JEDEC Specification MO-187 Variations AA.
(6) Lead span/stand off height/coplanarity are considered as special characteristics. (S)
(7) Controlling dimensions in inches. [mm]
Doc No. 3009, Rev. K
17
CAT1021, CAT1022, CAT1023
TDFN 3X3 PACKAGE (RD4, ZD4)
0.75 + 0.05
A
8
5
B
2X
2X
0.15
C
1
4
3.00 + 0.10
(S)
0.0 - 0.05
0.15
C
PIN 1 INDEX AREA
5
8
0.75 + 0.05
2.30 + 0.10
C0.35
C
0.25 min.
PIN 1 ID
0.30 + 0.10 (8x)
1
0.30 + 0.07 (8x)
0.65 TYP. (6x)
1.95 REF. (2x)
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY SHALL NOT EXCEED 0.08 mm.
3. WARPAGE SHALL NOT EXCEED 0.10 mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S)
5. REFER JEDEC MO-229 / WEEC
Doc. No. 3009, Rev. K
18
CAT1021, CAT1022, CAT1023
Ordering Information
Prefix
Device #
1021
Suffix
-30
TE13
CAT
J
I
Optional
Company ID
Temperature Range
I = Industrial (-40˚C to 85˚C)
E = Extended (-40˚C to +125˚C)
Tape & Reel
Product
Number
1021: 2K
1022: 2K
1023: 2K
SOIC: 2000/Reel
TSSOP: 2000/Reel
MSOP: 2500/Reel
TDFN: 2000/Reel
Package
ResetThreshold
P: PDIP
J: SOIC
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
R: MSOP
U: TSSOP
RD4: 8-pad TDFN (3x3mm)
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
ZD4: TDFN 3x3mm (Lead free, Halogen free)
Note:
2
(1) The device used in the above example is a CAT1021JI-30TE13 (Supervisory circuit with I C serial 2k CMOS EEPROM, SOIC, Industrial
Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).
Doc No. 3009, Rev. K
19
REVISION HISTORY
Date
Rev.
Reason
9/25/2003
F
Added Green Package logo
Updated DC Operating Characteristic notes
Updated Reliability Characteristics notes
Eliminated Automotive temperature range
11/7/2003
G
Updated Ordering Information with “Green” package
codes
Updated Reset Circuit AC Characteristics
Eliminated data sheet designation
Updated Reel Ordering Information
Eliminated 8-pad TDFN package (3x4.9mm)
Changed SOIC package designators
Added package outlines
4/12/2004
11/1/2004
H
I
11/04/04
11/11/04
J
Update Pin Configuration
K
Update Features
Update Description
Updae DC Operating Characteristic
Update AC Characteristics
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
AE ™
I2C is a trademark of Philips Corporation
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 3009
Revison:
Issue date:
Type:
K
11/11/04
Preliminary
www.catalyst-semiconductor.com
CAT1022LI-45TE13 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
CAT1022LI25 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, 0.300 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, DIP-8 | 获取价格 | |
CAT1022LI28 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, 0.300 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, DIP-8 | 获取价格 | |
CAT1022LI30 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, 0.300 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, DIP-8 | 获取价格 | |
CAT1022LI42 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, 0.300 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, DIP-8 | 获取价格 | |
CAT1022LI45 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, 0.300 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, DIP-8 | 获取价格 | |
CAT1022PA-25 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, PLASTIC, DIP-8 | 获取价格 | |
CAT1022PA-28 | CATALYST | Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDIP8, PLASTIC, DIP-8 | 获取价格 | |
CAT1022PA-28 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, PLASTIC, DIP-8 | 获取价格 | |
CAT1022PA-30 | CATALYST | Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDIP8, PLASTIC, DIP-8 | 获取价格 | |
CAT1022PA-30 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, PLASTIC, DIP-8 | 获取价格 |
CAT1022LI-45TE13 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6