CAT1022WI-45-T2
更新时间:2024-09-18 06:14:08
品牌:CATALYST
描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
CAT1022WI-45-T2 概述
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer 监控电路,带有I2C串行2K位CMOS EEPROM ,手动复位及看门狗定时器
CAT1022WI-45-T2 数据手册
通过下载CAT1022WI-45-T2数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CAT1021, CAT1022, CAT1023
Supervisory Circuits with I2C Serial 2k-bit CMOS
EEPROM, Manual Reset and Watchdog Timer
FEATURES
DESCRIPTION
ꢀ Precision Power Supply Voltage Monitor
— 5V, 3.3V and 3V systems
The CAT1021, CAT1022 and CAT1023 are complete
memory and supervisory solutions for microcontroller-
based systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection are
integrated together in low power CMOS technology.
Memory interface is via a 400kHz I2C bus.
— Five threshold voltage options
ꢀ Watchdog Timer
ꢀ Active High or Low Reset
— Valid reset guaranteed at VCC = 1V
ꢀ 400kHz I2C Bus
The CAT1021 and CAT1023 provide a precision VCC
sense circuit and two open drain outputs: one (RESET)
¯¯¯¯¯¯
drives high and the other (RESET) drives low whenever
ꢀ 2.7V to 5.5V Operation
VCC falls below the reset threshold voltage. The
ꢀ Low power CMOS technology
ꢀ 16-Byte Page Write Buffer
ꢀ Built-in inadvertent write protection
— WP pin (CAT1021)
¯¯¯¯¯¯
CAT1022 has only a RESET output and does not have
a Write Protect input. The CAT1021 also has a Write
Protect input (WP). Write operations are disabled if WP
is connected to a logic high.
All supervisors have a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. For the
CAT1021 and CAT1022, the watchdog timer monitors
the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.
ꢀ 1,000,000 Program/Erase cycles
ꢀ Manual Reset Input
ꢀ 100 year data retention
ꢀ Industrial and extended temperature ranges
ꢀ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply voltage
exceeds the reset threshold level. With both active high
and low reset signals, interface to microcontrollers and
(3 x 3mm foot-print) packages
— TDFN max height is 0.8mm
¯¯¯¯¯¯
other ICs is simple. In addition, the RESET pin or a
¯¯¯
separate input, MR, can be used as an input for push-
button manual reset capability.
For Ordering Information details, see page 19.
The on-chip, 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided
by a VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until VCC
reaches the reset threshold during power up.
Available packages include an 8-pin DIP and surface
mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin
MSOP packages. The TDFN package thickness is
0.8mm maximum. TDFN footprint options are 3 x 3mm.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
BLOCK DIAGRAM
THRESHOLD VOLTAGE OPTION
EXTERNAL LOAD
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
SENSEAMPS
SHIFT REGISTERS
D
OUT
ACK
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
V
CC
WORDADDRESS
BUFFERS
COLUMN
DECODERS
V
SS
START/STOP
SDA
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
WP
(CAT1021)
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
Vcc Monitor
SLAVE
ADDRESS
COMPARATORS
MR
WDI
(CAT1023)
RESET
(CAT1021/23)
RESET
PIN CONFIGURATION
DIP Package (L)
(Bottom View)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (ZD4)
¯¯¯
MR
VCC
RESET
SCL
8
7
6
5
1
2
3
4
¯¯¯
MR
1
2
3
4
8
7
6
5
VCC
¯¯¯¯¯¯
RESET
CAT1021
CAT1022
CAT1023
¯¯¯¯¯¯
RESET
RESET
SCL
CAT1021
CAT1022
CAT1023
WP
VSS
WP
VSS
SDA
SDA
¯¯¯
MR
VCC
8
1
¯¯¯
MR
1
2
3
4
8
7
6
5
VCC
¯¯¯¯¯¯
RESET
NC
SCL
SDA
7
6
5
2
3
4
¯¯¯¯¯¯
RESET
NC
NC
VSS
NC
VSS
SCL
SDA
¯¯¯
MR
VCC
WDI
SCL
SDA
8
7
6
5
1
2
3
4
¯¯¯
MR
1
2
3
4
8
7
6
5
VCC
¯¯¯¯¯¯
RESET
¯¯¯¯¯¯
RESET
WDI
SCL
SDA
RESET
VSS
RESET
VSS
Doc. No. MD-3009 Rev. M
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
PIN FUNCTION
PIN DESCRIPTION
¯¯¯¯¯¯
(RESET CAT1021/23 Only)
Pin
Name
RESET/RESET: RESET OUTPUT
Function
¯¯¯¯¯¯
These are open drain pins and RESET can be used
as a manual reset trigger input. By forcing a reset
condition on the pin the device will initiate and
maintain a reset condition. The RESET pin must be
connected through a pull-down resistor, and the
¯¯¯¯¯¯
resistor.
NC
No Connect
¯¯¯¯¯¯
RESET
Active Low Reset Input/Output
Ground
VSS
SDA
SCL
Serial Data/Address
Clock Input
RESET pin must be connected through a pull-up
RESET Active High Reset Output (CAT1021/23)
SDA: SERIAL DATA ADDRESS
VCC
WP
Power Supply
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
Write Protect (CAT1021 only)
Manual Reset Input
¯¯¯
MR
WDI
Watchdog Timer Interrupt (CAT1023)
SCL: SERIAL CLOCK
Serial clock input.
OPERATING TEMPERATURE RANGE
¯¯¯
MR: MANUAL RESET INPUT
Industrial
-40ºC to 85ºC
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset
condition. Reset outputs are active while MR input is
low and for the reset timeout period after MR returns
to high. The input has an internal pull up resistor.
Extended -40ºC to 125ºC
WP (CAT1021 Only): WRITE PROTECT INPUT
When WP input is tied to VSS or left unconnected write
operations to the entire array are allowed. When tied
to VCC, the entire array is protected. This input has an
internal pull down resistor.
WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low
to high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
CAT102X FAMILY OVERVIEW
Manual
Reset
Input Pin
Watchdog
Monitor
Pin
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET:
Active High
and LOW
Device
Watchdog
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
SDA
SDA
WDI
2k
2k
2k
2k
2k
2k
2k
ꢁ ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ ꢁ
ꢁ ꢁ
ꢁ ꢁ
ꢁ
ꢁ
ꢁ ꢁ
ꢁ
WDI
ꢁ
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
–55 to +125
–65 to +150
–2.0 to VCC + 2.0
–2.0 to 7.0
1.0
Units
ºC
ºC
V
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current(3)
W
300
ºC
mA
100
D.C. OPERATING CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol Parameter
Test Conditions
VIN = GND to VCC
VIN = GND to VCC
Min
-2
Typ
Max
10
Units
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
-10
10
µA
f
SCL = 400kHz
ICC1
ICC2
ISB
Power Supply Current (Write)
3
1
mA
mA
µA
VCC = 5.5V
fSCL = 400kHz
Power Supply Current (Read)
Standby Current
VCC = 5.5V
Vcc = 5.5V,
VIN = GND or VCC
60
(4)
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3 x VCC
VCC + 0.5
V
V
(4)
0.7 x VCC
I
OL = 3mA
VOL
VOH
0.4
V
V
V
¯¯¯¯¯¯
(SDA, RESET)
VCC = 2.7V
Output High Voltage
(RESET)
IOH = -0.4mA
VCC = 2.7V
Vcc - 0.75
4.50
CAT102x-45
(VCC = 5.0V)
4.75
4.50
3.15
3.00
2.70
CAT102x-42
(VCC = 5.0V)
4.25
CAT102x-30
(VCC = 3.3V)
VTH
Reset Threshold
3.00
CAT102x-28
(VCC = 3.3V)
2.85
CAT102x-25
(VCC = 3.0V)
2.55
VRVALID
Reset Output Valid VCC Voltage
Reset Threshold Hysteresis
1.00
15
V
(5)
VRT
mV
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) VIL min and VIH max are reference values only and are not tested.
(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol Test
Test Conditions
VOUT = 0V
Max
8
Units
pF
(1)
COUT
Output Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6
pF
AC CHARACTERISTICS
CC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
V
Memory Read & Write Cycle(2)
Symbol Parameter
Min
Max
400
100
Units
kHz
ns
fSCL
tSP
tLOW
tHIGH
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
1.3
0.6
µs
Clock High Period
µs
(1)
tR
SDA and SCL Rise Time
300
300
ns
(1)
tF
SDA and SCL Fall Time
ns
tHD; STA
tSU; STA
tHD; DAT
tSU; DAT
tSU; STO
tAA
Start Condition Hold Time
0.6
0.6
0
µs
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
µs
ns
Data Input Setup Time
100
0.6
ns
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
µs
900
5
ns
tDH
50
ns
(1)
tBUF
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
µs
(3)
tWC
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
RESET CIRCUIT AC CHARACTERISTICS
Symbol
tPURST
tRDP
Parameter
Test Conditions
Note 2
Min
Typ
Max
270
5
Units
ms
µs
Power-Up Reset Timeout
VTH to RESET output Delay
VCC Glitch Reject Pulse Width
130
200
Note 3
tGLITCH
Note 4, 5
Note 1
30
ns
MR Glitch Manual Reset Glitch Immunity
100
ns
tMRW
tMRD
tWD
MR Pulse Width
Note 1
5
µs
MR Input to RESET Output Delay
Watchdog Timeout
Note 1
1
µs
Note 1
1.0
1.6
2.1
sec
POWER-UP TIMING (5), (6)
Symbol
tPUR
Parameter
Test Conditions
Min
Typ
Max
270
270
Units
ms
Power-Up to Read Operation
Power-Up to Write Operation
tPUW
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
Input Rise and Fall times
Input Reference Voltages
Output Reference Voltages
Output Load
0.2VCC to 0.8VCC
10ns
0.3VCC , 0.7VCC
0.5VCC
Current Source: IOL = 3mA; CL = 100pF
RELIABILITY CHARACTERISTICS
Symbol Parameter
Reference Test Method
Min
Max
Units
(5)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
Cycles/Byte
Years
(5)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(5)
VZAP
2000
Volts
(5)(7)
ILTH
100
mA
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
Doc. No. MD-3009 Rev. M
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
DEVICE OPERATION
¯¯¯
are required. Manual reset operation using MR input
is shown in Figure 2.
Reset Controller Description
The CAT1021/22/23 precision RESET controllers
ensure correct system operation during brownout and
power up/down conditions. They are configured with
open drain RESET outputs.
Hardware Data Protection
The CAT1021/22/23 supervisors have been designed
to solve many of the data corruption issues that have
long been associated with serial EEPROMs. Data
corruption occurs when incorrect data is stored in a
memory location which is assumed to hold correct data.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST
)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal non-
volatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5ms) before VCC reaches the minimum value of 2V.
During power-down, the RESET outputs will be active
¯¯¯¯¯¯
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designed to ignore the fast negative going VCC
transient pulses (glitches).
Reset output timing is shown in Figure 1.
In addition, the CAT1021 includes a Write Protection
Input which when tied to VCC will disable any write
operations to the device.
Manual Reset Operation
¯¯¯¯¯¯
The RESET pin can operate as reset output and
manual reset input. The input is edge triggered; that
¯¯¯¯¯¯
is, the RESET input will initiate a reset timeout after
Watchdog Timer
detecting a high to low transition.
The Watchdog Timer provides an independent
protection for microcontrollers. During a system
failure, CAT1021/22/23 devices will provide a reset
signal after a time-out interval of 1.6 seconds for a
lack of activity. The CAT1023 is designed with the
Watchdog timer feature on the WDI pin. The CAT1021
and CAT1022 monitor the SDA line. If WDI or SDA
does not toggle within a 1.6 second interval, the reset
condition will be generated on the reset outputs. The
watchdog timer is cleared by any transition on a
monitored line.
¯¯¯¯¯¯
When RESET I/O is driven to the active state, the 200
msec timer will begin to time the reset interval. If
external reset is shorter than 200ms, Reset outputs
will remain active at least 200ms.
The CAT1021/22/23 also have a separate manual
reset input. Driving the MR input low by connecting a
pushbutton (normally open) from MR pin to GND will
generate a reset condition. The input has an internal
pull up resistor.
¯¯¯
¯¯¯
As long as reset signal is asserted, the watchdog
timer will not count and will stay cleared.
¯¯¯
Reset remains asserted while MR is low and for the
¯¯¯
Reset Timeout period after MR input has gone high.
¯¯¯
Glitches shorter than 100ns on MR input will not ge-
nerate a reset pulse. No external debouncing circuits
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
Figure 1. RESET Output Timing
tGLITCH
VTH
V
RVALID
tRPD
tPURST
VCC
tRPD
tPURST
RESET
RESET
Figure 2: ¯M¯R¯ Operation and Timing
tMRW
MR
tMRD
tPURST
RESET
RESET
Doc. No. MD-3009 Rev. M
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
SDA when SCL is HIGH. The CAT1021/22/23 monitor
the SDA and SCL lines and will not respond until this
condition is met.
EMBEDDED EEPROM OPERATION
The CAT1021/22/23 feature a 2-kbit embedded serial
EEPROM that supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master
device which generates the serial clock and all
START and STOP conditions for bus access. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls
which mode is activated.
STOP CONDITION
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
programmable in metal and the default is 1010.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
After the Master sends a START condition and the
slave address byte, the CAT1021/22/23 monitors the
bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
address. The CAT1021/22/23 then perform a Read or
START CONDITION
¯¯
Write operation depending on the R/W bit.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 3. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
¯¯
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknow-
ledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The device acknowledges once more and the Master
generates the STOP condition. At this time, the device
begins an internal programming cycle to non-volatile
memory. While the cycle is in progress, the device will
not respond to any request from the Master device.
All devices respond with an acknowledge after
receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When a device begins a READ mode it transmits 8
bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the device will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7: Slave Address Bits
Default Configuration
1
0
1
0
0
0
0
R/W
Doc. No. MD-3009 Rev. M
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
Page Write
The CAT1021/22/23 writes up to 16 bytes of data in
a single write cycle, using the Page Write operation.
The page write operation is initiated in the same
manner as the byte write operation, however instead
of terminating after the initial byte is transmitted, the
Master is allowed to send up to 15 additional bytes.
After each byte has been transmitted, the
CAT1021/22/23 will respond with an acknowledge
and internally increment the lower order address bits
by one. The high order bits remain unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1021/22/23 in a single write cycle.
Figure 8. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 9: Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
Acknowledge Polling
READ OPERATIONS
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1021/22/23 initiates
the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the device is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
The READ operation for the CAT1021/22/23 is initiated in
the same manner as the write operation with one
¯¯
exception, the R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1021 only) allows
the user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
memory array is protected and becomes read only.
The CAT1021 will accept both slave and byte addre-
sses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVIT Y:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. MD-3009 Rev. M
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
Immediate/Current Address Read
Sequential Read
The CAT1021/22/23 address counter contains the
address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE
access was to address N, the READ immediately
following would access data from address N + 1. For
N = E = 255, the counter will wrap around to zero
and continue to clock out valid data. After the
CAT1021/22/23 receives its slave address infor-
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1021/22/23 sends the inital 8-
bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data. The CAT1021/22/23 will continue to output an 8-
bit byte for each acknowledge, thus sending the STOP
condition.
¯¯
mation (with the R/W bit set to one), it issues an
The data being transmitted from the CAT1021/22/23 is
sent sequentially with the data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT1021/22/23
address bits so that the entire memory array can be
read during one operation.
acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1021/22/23 acknowledges, the Master device
sends the START condition and the slave address
¯¯
again, this time with the R/W bit set to one. The
CAT1021/22/23 then responds with its acknowledge
and sends the 8-bit byte requested. The master
device does not send an acknowledge but will
generate a STOP condition.
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L)(1)(2)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
Doc. No. MD-3009 Rev. M
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
(1)(2)
SOIC 8-Lead 150mils (W)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
4.80
5.80
3.80
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
TSSOP 8-Lead (V) (1)(2)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.40
E
E1
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.75
8°
e
TOP VIEW
D
c
A2
A
θ1
A1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153
Doc. No. MD-3009 Rev. M
16
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
MSOP 8-Lead (Z) (1)(2)
SYMBOL
MIN
NOM
MAX
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
A
A1
A2
b
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E
E1
E1
e
3.00
0.65 BSC
0.60
L
0.40
0º
0.80
6º
L1
L2
θ
0.95 REF
0.25 BSC
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
θ
L2
L
L1
DETAIL A
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
17
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
TDFN 8-Pad 3 x 3mm (ZD4) (1)(2)
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
0.75
MAX
0.80
0.05
A
A
A1
A3
b
0.70
0.00
A3
0.02
A1
0.20 REF
0.30
FRONT VIEW
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.50
3.10
1.80
D
3.00
D2
E
—
3.00
E2
e
—
0.65TYP
0.30
L
0.20
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
Doc. No. MD-3009 Rev. M
18
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1021, CAT1022, CAT1023
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device # Suffix
CAT
1021
W
I
-30
–
G T3
Temperature Range
Tape & Reel
Company ID
T: Tape & Reel
2: 2000/Reel (only TDFN)
3: 3,000/Reel
I = Industrial (-40ºC to 85ºC)
Product
Number
1021: 2K
1022: 2K
1023: 2K
Package
Reset Threshold Voltage
-45: 4.50V – 4.75V
-42: 4.25V – 4.50V
-30: 3.00V – 3.15V
-28: 2.85V – 3.00V
-25: 2.55V – 2.70V
L: PDIP
W: SOIC
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Y: TSSOP
Z: MSOP
ZD4: TDFN 3x3mm (5)
Ordering Part Number – CAT1021xx
CAT1021LI-45-G
CAT1021ZI-45-GT3
CAT1021LI-42-G
CAT1021ZI-42-GT3
CAT1021ZI-30-GT3
CAT1021ZI-28-GT3
CAT1021ZI-25-GT3
CAT1021ZD4I-45-T2
CAT1021ZD4I-42-T2
CAT1021ZD4I-30-T2
CAT1021ZD4I-28-T2
CAT1021ZD4I-25-T2
CAT1021LI-30-G
CAT1021LI-28-G
CAT1021LI-25-G
CAT1021WI-45-GT3
CAT1021WI-42-GT3
CAT1021WI-30-GT3
CAT1021WI-28-GT3
CAT1021WI-25-GT3
CAT1021YI-45-GT3
CAT1021YI-42-GT3
CAT1021YI-30-GT3
CAT1021YI-28-GT3
CAT1021YI-25-GT3
CAT1022xx and Cat1023xx Ordering Part Numbers are located on page 20.
For Product Top Mark Codes, click here:
http://www.catsemi.com/techsupport/producttopmark.asp
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT1021WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel,
3,000/Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(5) TDFN not available in NiPdAu (–G) version.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
19
Doc. No. MD-3009 Rev. M
CAT1021, CAT1022, CAT1023
Ordering Part Number – CAT1022xx
CAT1022LI-45-G
CAT1022ZI-45-GT3
CAT1022LI-42-G
CAT1022ZI-42-GT3
CAT1022ZI-30-GT3
CAT1022ZI-28-GT3
CAT1022ZI-25-GT3
CAT1022ZD4I-45-T2
CAT1022ZD4I-42-T2
CAT1022ZD4I-30-T2
CAT1022ZD4I-28-T2
CAT1022ZD4I-25-T2
CAT1022LI-30-G
CAT1022LI-28-G
CAT1022LI-25-G
CAT1022WI-45-GT3
CAT1022WI-42-GT3
CAT1022WI-30-GT3
CAT1022WI-28-GT3
CAT1022WI-25-GT3
CAT1022YI-45-GT3
CAT1022YI-42-GT3
CAT1022YI-30-GT3
CAT1022YI-28-GT3
CAT1022YI-25-GT3
Ordering Part Number – CAT1023xx
CAT1023LI-45-G
CAT1023ZI-45-GT3
CAT1023LI-42-G
CAT1023ZI-42-GT3
CAT1023ZI-30-GT3
CAT1023ZI-28-GT3
CAT1023ZI-25-GT3
CAT1023ZD4I-45-T2
CAT1023ZD4I-42-T2
CAT1023ZD4I-30-T2
CAT1023ZD4I-28-T2
CAT1023ZD4I-25-T2
CAT1023LI-30-G
CAT1023LI-28-G
CAT1023LI-25-G
CAT1023WI-45-GT3
CAT1023WI-42-GT3
CAT1023WI-30-GT3
CAT1023WI-28-GT3
CAT1023WI-25-GT3
CAT1023YI-45-GT3
CAT1023YI-42-GT3
CAT1023YI-30-GT3
CAT1023YI-28-GT3
CAT1023YI-25-GT3
Doc. No. MD-3009 Rev. M
20
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Reason
9/25/2003
F
Added Green Package logo
Updated DC Operating Characteristic notes
Updated Reliability Characteristics notes
11/7/2003
G
Eliminated Automotive temperature range
Updated Ordering Information with “Green” package codes
Updated Reset Circuit AC Characteristics
4/12/2004
11/1/2004
H
I
Eliminated data sheet designation
Updated Reel Ordering Information
Eliminated 8-pad TDFN package (3 x 4.9mm)
Changed SOIC package designators
Added package outlines
11/04/2004
11/11/2004
J
K
L
Update Pin Configuration
Update Feature
Update Description
Update DC Operating Characteristic
Update AC Characteristics
02/02/2007
11/28/2007
Update Example of Ordering Information
Update Package Outline Drawings
Update Example of Ordering Information
Add “MD-“ to document number
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where
personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: MD-3009
Revision:
M
Issue date:
11/28/07
CAT1022WI-45-T2 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
CAT1022WI-45-T3 | CATALYST | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer | 获取价格 | |
CAT1022WI-45T2 | CATALYST | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer | 获取价格 | |
CAT1022WI-45T3 | CATALYST | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer | 获取价格 | |
CAT1022WI-45TE13 | CATALYST | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer | 获取价格 | |
CAT1022WI-45TE13 | ONSEMI | IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD AND HALOGEN FREE, SOIC-8, Power Management Circuit | 获取价格 | |
CAT1022WI25 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOIC-8 | 获取价格 | |
CAT1022WI30 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOIC-8 | 获取价格 | |
CAT1022YE-25 | CATALYST | Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO8, LEAD AND HALOGEN FREE, TSSOP-8 | 获取价格 | |
CAT1022YE-25TE13 | CATALYST | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer | 获取价格 | |
CAT1022YE-28 | ONSEMI | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD AND HALOGEN FREE, TSSOP-8 | 获取价格 |
CAT1022WI-45-T2 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6