CAT1162JI-42 [CATALYST]
Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO8, SOIC-8;
| 型号： | CAT1162JI-42 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO8, SOIC-8 光电二极管 |
| 文件： | 总12页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT1161/2 (16K)
Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer
FEATURES
■ Active high or low reset
■ Watchdog monitors SDA signal (CAT1161)
■ 400kHz I2C bus compatible
■ 2.7V to 6.0V operation
— Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
■ 1,000,000 Program/Erase cycles
■ Manual Reset
■ Low power CMOS technology
■ 16-Byte page write buffer
■ Built-in inadvertent write protection
— VCC lock out
■ 100 Year data retention
■ 8-pin DIP or 8-pin SOIC
— Write protect pin, WP
■ Commercial and industrial temperature ranges
DESCRIPTION
voltages support 5V, 3.3V and 3V systems. If power supply
voltages are out of tolerance reset signals become active,
preventing the system microcontroller, ASIC or peripherals
from operating. Reset signals become inactive typically 200
ms after the supply voltage exceeds the reset threshold
level. With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. In addition, a
reset pin can be used as a debounced input for push-button
manual reset capability.
The CAT1161/2 is a complete memory and supervisory
solution for microcontroller-based systems. A serial
EEPROM memory (16K) with hardware memory write
protection, a system power supervisor with brown out
protectionandawatchdogtimerareintegratedtogether
inlowpowerCMOStechnology. Memoryinterfaceisvia
an I2C bus.
The 1.6-second watchdog circuit returns a system to a
known good state if a software or hardware glitch halts
or“hangs”thesystem.TheCAT1161watchdogmonitors
the SDA line, making an additional PC board trace
unnecessary. The lower cost CAT1162 does not have a
watchdog timer.
TheCAT1161/2memoryfeaturesa16-bytepage.Inaddition,
hardware data protection is provided by a write protect pin
WP and by a VCC sense circuit that prevents writes to
memory whenever VCC falls below the reset threshold or
until VCC reaches the reset threshold during power up.
Available packages include an 8-pin DIP and a surface
mount, 8-pin SO package.
The power supply monitor and reset circuit protects
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
BLOCK DIAGRAM
PIN CONFIGURATION
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
D
OUT
ACK
V
DC
CC
V
CC
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
RESET
GND
RESET
CAT1161/2
SCL
WP
GND
START/STOP
LOGIC
SDA
SDA
16K
EEPROM
XDEC
CONTROL
LOGIC
DC = Do not connect
WP
Part Dash Minimum Maximum
Number Threshold Threshold
DATA IN STORAGE
-45
-42
4.50
4.25
4.75
4.50
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
-30
-28
-25
3.00
2.85
2.55
3.15
3.00
2.70
Precision
SLAVE
ADDRESS
COMPARATORS
WATCHDOG
Only for
CAT1161
Vcc Monitor
RESET RESET
© 2002 by Catalyst Semiconductor, Inc.
Doc No. 3002, Rev. D
Characteristics subject to change without notice
CAT1161/2
PIN FUNCTIONS
ABSOLUTE MAXIMUM RATINGS
Pin No. Pin Name Function
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
1
2
DC
Do Not Connect
RESET
Active Low Reset I/O
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
3
4
5
6
7
8
WP
GND
SDA
Write Protect
Ground
V
CC with Respect to Ground ............... –2.0V to +7.0V
Serial Data/Address
Clock Input
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
SCL
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RESET
VCC
Active High Reset I/O
Power Supply
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
(3)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
Cycles/Byte
Years
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
(3)
VZAP
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
= +2.7V to +6.0V, unless otherwise specified.
V
CC
Symbol
ICC
Parameter
Test Conditions
Min
Typ
Max
Units
Power Supply Current
Standby Current
fSCL = 100 KHz
3
mA
ISB
VCC = 3.3V
VCC = 5
40
50
µA
µA
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC
VIN = GND or VCC
2
µA
µA
ILO
VIL
VIH
VOL1
10
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
Input High Voltage
VCC X 0.7
Output Low Voltage (SDA) IOL = 3 mA, VCC = 3.0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 3002, Rev. D
2
CAT1161/2
CAPACITANCE
T = 25˚C, f = 1.0 MHz, V
A
= 5V
CC
Symbol Test
Conditions
VI/O = 0V
VIN = 0V
Max
8
Units
pF
(1)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
(1)
CIN
6
pF
A.C. CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF.
VCC = 2.7V - 6V
VCC = 4.5V - 5.5V
SYMBOL PARAMETER
Min
Max
100
200
Min
Max
400
200
Units
kHz
ns
FSCL
TI(1)
Clock Frequency
Noise Suppresion Time
Constant at SCL, SDA Inputs
SLC Low to SDA Data Out
and ACK Out
tAA
3.5
1
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
0.6
1.2
0.6
0.6
µs
µs
µs
µs
4.7
4
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
tHD:DAT
tSU:DAT
Data in Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data in Setup Time
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
POWER-UP TIMING
Symbol Parameter
Max
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
WRITE CYCLE LIMITS
Symbol Parameter
Min
Typ
Max
Units
ms
tWR
Write Cycle Time
10
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)
t
and t
are the delays required from the time V is stable until the specific operation can be initiated.
PUR
PUW
CC
Doc No. 3002, Rev. D
3
CAT1161/2
RESET CIRCUIT CHARACTERISTICS
Symbol
tGLITCH
VRT
Parameter
Min
Typ
Max
Units
ns
Glitch Reject Pulse Width
Reset Threshold Hystersis
Reset Output Low Voltage (IOLRS=1mA)
100
15
mV
V
VOLRS
VOHRS
0.4
Reset Output High Voltage
Reset Threshold (VCC=5V)
(CAT1161/2-45)
VCC-0.75
4.50
V
4.75
Reset Threshold (VCC=5V)
(CAT1161/2-42)
4.25
3.00
2.85
2.55
130
4.50
3.15
3.00
2.70
270
Reset Threshold (VCC=3.3V)
(CAT1161/2-30)
V
VTH
Reset Threshold (VCC=3.3V)
(CAT1161/2-28)
Reset Threshold (VCC=3V)
(CAT1161/2-25)
tPURST
twp
Power-Up Reset Timeout
Watchdog Period
ms
sec
µs
1.6
tRPD
VTH to RESET Output Delay
RESET Output Valid
5
VRVALID
1
V
Doc. No. 3002, Rev. D
4
CAT1161/2
PIN DESCRIPTIONS
WP:
WRITE PROTECT
remain active until VCC reaches the VTH threshold and will
If the pin is tied to VCC the entire memory array
becomes Write Protected (READ only). When the pin
is tied to GND or left floating normal read/write
operations are allowed to the device.
continuedrivingtheoutputsforapproximately200ms(tPURST
)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this point the
resetoutputswillbepulledupordownbytheirrespectivepull
up/down resistors. During power-down, the RESET outputs
will be active when VCC falls below VTH. The RESET outputs
will be valid so long as VCC is >1.0V (VRVALID).
RESET/RESET: RESET I/O
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins
the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-
down resistor, and the RESET pin must be connected
through a pull-up resistor.
The RESET pins are I/Os; therefore, the CAT1161/2 can act
as a signal conditioning circuit for an externally applied
manual reset. The inputs are edge triggered; that is, the
RESET input in the CAT1161/2 will initiate a reset timeout
after detecting a low to high transition and the RESET input
will initiate a reset timeout after detecting a high to low
transition.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
Watchdog Timer
TheWatchdogTimerprovidesanindependentprotectionfor
microcontrollers. During a system failure, the CAT1161will
respond with a reset signal after a time-out interval of 1.6
seconds for a lack of activity. The CAT1161 is designed with
the Watchdog Timer feature on the SDA input. If the
microcontroller does not toggle the SDA input pin within 1.6
seconds, the Watchdog Timer times out. This will generate
a reset condition on reset outputs. The Watchdog Timer is
cleared by any transition on SDA.
If there is no transition on the SDA for more than 1.6
seconds, the watchdog timer times out.
SCL: SERIAL CLOCK
Serial clock input.
DEVICE OPERATION
Reset Controller Description
As long as the reset signal is asserted, the Watchdog Timer
will not count and will stay cleared.
The CAT1161/2 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain The CAT1162 does not have a Watchdog.
RESET outputs. During power-up, the RESET outputs
t
Figure 1. RESET Output Timing
GLITCH
V
TH
V
RVALID
V
CC
t
RPD
t
t
PURST
PURST
RESET
t
RPD
RESET
Doc No. 3002, Rev. D
5
CAT1161/2
Hardware Data Protection
falls below (power down) VTH or until VCC reaches the
reset threshold (power up) VTH. Any attempt to access
the internal EEPROM is not recognized and an ACK will
not be sent on the SDA line when RESET or RESET
is active.
The CAT1161/2 is designed with the following hardware
data protection features to provide a high degree of data
integrity.
Reset Threshold Voltage
(1)TheCAT1161/2featuresaWPpin. WhentheWPpin
is tied high the entire memory array becomes write
protected (read only).
The CAT1161/2 is offered with five reset threshold
voltage ranges. They are 4.50-4.75V, 4.25-4.50V, 3.00-
3.15V, 2.85-3.00V and 2.55-2.70V.
(2) The VCC sense provides write protection when VCC
fallsbelowtheresetthresholdvalue(VTH).TheVCC lock
out inhibits writes to the serial EEPROM whenever VCC
Figure 2. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 3. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 4. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 3002, Rev. D
6
CAT1161/2
FUNCTIONAL DESCRIPTION
STOP Condition
The CAT1161/2 supports the I2C Bus data transmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. Both the Master device and
Slavedevicecanoperateaseithertransmitterorreceiver,
but the Master device controls which mode is activated.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition.TheMastersendstheaddressoftheparticular
slave device it is requesting. The four most significant
bits of the 8-bit slave address are fixed as 1010.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
Thenextthreebits(Figure6)definememoryaddressing.
For the CAT1161/162 the three bits define higher order
bits.
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
ReadorWriteoperationistobeperformed.Whenthisbit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT1161/2 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1161/2 then performs a Read or Write operation
depending on the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT1161/2 monitors the
SDA and SCL lines and will not respond until this
condition is met.
Figure 5. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 6. Slave Address Bits
CAT1161/2
1
0
1
0
a10 a9
a8 R/W
**a8, a9 and a10 correspond to the address of the memory array address word.
Doc No. 3002, Rev. D
7
CAT1161/2
ACKNOWLEDGE
pointers of the CAT1161/2. After receiving another
acknowledgefromtheSlave,theMasterdevicetransmits
thedatatobewrittenintotheaddressedmemorylocation.
TheCAT1161/2acknowledgesoncemoreandtheMaster
generates the STOP condition. At this time, the device
begins an internal programming cycle to non-volatile
memory. While the cycle is in progress, the device will not
respond to any request from the Master device.
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT1161/2 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress.Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Page Write
The CAT1161/2 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the byte
write operation, however instead of terminating after the
initial byte is transmitted, the Master is allowed to send up
to 15 additional bytes. After each byte has been
transmitted, the CAT1161/2 will respond with an
acknowledge and internally increment the lower order
addressbitsbyone.Thehighorderbitsremainunchanged.
When the CAT1161/2 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1161/2 will continue to transmit
data.IfnoacknowledgeissentbytheMaster,thedevice
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
IftheMastertransmitsmorethan16bytesbeforesending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1161/2 in a single write cycle.
Figure 7. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc. No. 3002, Rev. D
8
CAT1161/2
Acknowledge Polling
protected and becomes read only. The CAT1161/2 will
accept both slave and byte addresses, but the memory
locationaccessedisprotectedfromprogrammingbythe
device’s failure to send an acknowledge after the first
byte of data is received.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issuedtoindicatetheendofthehost’swriteopration, the
CAT1161/2 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation. If the CAT1161/2 is still busy with the write
operation, no ACK will be returned. If a write operation
hascompleted, anACKwillbereturnedandthehostcan
then proceed with the next read or write operation.
Read Operations
TheREADoperationfortheCAT1161/2isinitiatedinthe
same manner as the write operation with one exception,
thatR/Wbitissettoone.ThreedifferentREADoperations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent memory array programming. If the
WP pin is tied to VCC, the entire memory array is
Figure 9. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc No. 3002, Rev. D
9
CAT1161/2
Immediate/Current Address Read
The data being transmitted from the CAT1161/2 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1.TheREADoperationaddress
counter increments all of the CAT1161/2 address bits
so that the entire memory array can be read during one
operation. If more than E (where E=2047 for the
CAT1161/162)bytesarereadout,thecounterwill‘wrap
around’ and continue to clock out data bytes.
The CAT1161/2 address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
addressN,theREADimmediatelyfollowingwouldaccess
datafromaddressN+1. Foralldevices, N=E=2047. The
counter will wrap around to Zero and continue to clock
out valid data for the 16K devices. After the CAT1161/
2receivesitsslaveaddressinformation(withtheR/Wbit
set to one), it issues an acknowledge, then transmits the
8-bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Manual Reset Operation
The CAT116x RESET or RESET pin can also be used
as a manual reset input.
Only the “active” edge of the manual reset input is
internallysensed.ThepositiveedgeissensedifRESET
is used as a manual reset input and the negative edge
is sensed if RESET is used as a manual reset input.
Selective/RandomRead
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After the CAT1161/2 acknowledges, the
MasterdevicesendstheSTARTconditionandtheslave
address again, this time with the R/W bit set to one. The
CAT1161/2 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
An internal counter starts a 200 ms count. During this
time, the complementary reset output will be kept in the
active state. If the manual reset input is forced active for
more than 200 ms, the complementary reset output will
switch back to the non active state after the 200 ms
expired, regardless for how long the manual reset input
is forced active.
The embedded EEPROM is disabled as long as a reset
conditionismaintainedonanyRESETpin.Iftheexternal
forcedRESET/RESET islongerthaninternalcontrolled
time-out period, tPURST, the memory will not respond
with an acknowledge for any access as long as the
manual reset input is active.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1161/2 sends the inital 8-bit
byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data. The CAT1161/2 will continue to output an 8-bit
byte for each acknowledge, thus sending the STOP
condition.
Figure 10. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Doc. No. 3002, Rev. D
10
CAT1161/2
Figure 11. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Ordering Information
Prefix
Device #
1162
Suffix
-30
CAT
J
I
TE13
Optional
Company ID
Temperature Range
Blank = Commercial (0˚ to 70˚C)
I = Industrial (-40˚ to 85˚C)
Product
Tape & Reel
TE13: 2000/Reel
Number
1161: 16K
1162: 16K
ResetThreshold
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
Package
P: PDIP
J: SOIC (JEDEC)
Note:
(1) The device used in the above example is a CAT1162JI-30TE13 (16K I2C Memory, SOIC, Industrial Temperature, 3.0-3.15V Reset
Threshold Voltage, Tape and Reel)
Doc No. 3002, Rev. D
11
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DPP ™
AE2 ™
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 3002
Revison:
Issue date:
Type:
D
03/29/02
Final
www.catalyst-semiconductor.com
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