CAT1321LI-30TDFN [CATALYST]
Supervisory Circuits with I2C Serial 32K CMOS EEPROM; 监控电路，带有I2C串行32K CMOS EEPROM
| 型号： | CAT1321LI-30TDFN |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Supervisory Circuits with I2C Serial 32K CMOS EEPROM |
| 文件： | 总18页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT1320, CAT1321
Supervisory Circuits with I2C Serial 32K CMOS EEPROM
E TM
R
FEATURES
I 3.0V to 5.5V operation
I Precision power supply voltage monitor
I Low power CMOS technology
I 64-Byte page write buffer
I 1,000,000 Program/Erase cycles
I 100 year data retention
— 5V, 3.3V and 3V systems
- +5.0V (+/- 5%, +/- 10%)
- +3.3V (+/- 5%, +/- 10%)
- +3.0V (+/- 10%)
I Active low reset, CAT1320
I Active high reset, CAT1321
I Valid reset guaranteed at VCC=1V
I 400kHz I2C bus
I 8-pin DIP, SOIC, TSSOP and TDFN packages
I Industrial temperature range
DESCRIPTION
active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset options,
interface to microcontrollers and other ICs is simple. In
addition, the RESET (CAT1320) pin can be used as an
input for push-button manual reset capability.
The CAT1320 and CAT1321 are complete memory and
supervisorysolutionsformicrocontroller-basedsystems.
A 32kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I2C bus.
The CAT1320 provides a precision VCC sense circuit
and drives an open drain output, RESET low whenever
VCC falls below the reset threshold voltage.
The CAT1320/21 memory features a 64-byte page. In
addition, hardware data protection is provided by a VCC
sense circuit that prevents writes to memory whenever VCC
falls below the reset threshold or until VCC reaches the reset
threshold during power up.
The CAT1321 provides a precision VCC sense circuit
thatdrivesanopendrainoutput, RESEThighwhenever
VCC falls below the reset threshold voltage.
Available packages include an 8-pin DIP, SOIC, TSSOP
and 4.9 x 3mm TDFN.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supplyvoltagesareoutoftoleranceresetsignalsbecome
PIN CONFIGURATION
TDFN PACKAGE: 4.9MM X 3MM
(RD2, ZD2)
PDIP (P, L) SOIC (J, W)
TSSOP (U, Y)
1
2
3
4
8
7
6
5
A0
A1
A2
V
CC
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
A0
A1
A2
V
CC
RESET
A0
A1
A2
V
CC
RESET
RESET
SCL
CAT1320
CAT1320
CAT1321
CAT1320
SCL
SCL
V
V
SDA
SS
SDA
V
SDA
SS
SS
1
2
3
4
A0
8
7
6
5
V
8
1
2
3
4
8
7
6
5
1
A0
V
CC
A0
V
CC
CC
A1
A2
RESET
SCL
RESET
A1
A2
A1
A2
7
6
5
2
3
4
RESET
CAT1321
CAT1321
SCL
SDA
SCL
SDA
V
V
V
SDA
SS
SS
SS
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 20585, Rev. 00
1
CAT1320, CAT1321
Advance Information
Threshold Voltage Options
BLOCK DIAGRAM — CAT1320, CAT1321
EXTERNAL LOAD
Part Dash Minimum Maximum
Number Threshold Threshold
SENSE AMPS
SHIFT REGISTERS
D
OUT
ACK
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
V
V
CC
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
SDA
LOGIC
32kbit
EEPROM
XDEC
OPERATING TEMPERATURE RANGE
CONTROL
LOGIC
Industrial
-40˚C to 85˚C
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
A0
A1
A2
SLAVE
ADDRESS
COMPARATORS
Vcc Monitor
RESET (CAT1320)
RESET (CAT1321)
PIN FUNCTIONS
Pin Name
RESET
VSS
Function
Active Low Reset Input/Output (CAT1320)
Ground
SDA
Serial Data/Address
Clock Input
SCL
RESET
VCC
Active High Reset Output (CAT1321)
Power Supply
PIN DESCRIPTION
RESET/RESET: RESET OUTPUTS
SCL: SERIAL CLOCK
These are open-drain pins and RESET can also be used Serial clock input.
asamanualresettriggerinput.Byforcingaresetcondition
on the pin the device will initiate and maintain a reset
condition. The RESET pin must be connected through a
pull-downresistorandtheRESETpinmustbeconnected
through a pull-up resistor.
A0, A1, A2:
DEVICE ADDRESS INPUTS
When hardwired, up to eight CAT1320/21 devices may
be addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the
default values are zeros.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to trans-
fer all data into and out of the device. The SDA pin is an
open drain output and can be wire-ORed with other open
drain or open collector outputs.
Doc. No. 25085, Rev. 00
2
Advance Information
CAT1320, CAT1321
Stresses above those listed under “Absolute Maximum Ratings” may
causepermanentdamagetothedevice. Thesearestressratingsonly,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .................... -40°C to +85°C
Storage Temperature........................ -65°C to +105°C
Voltage on any Pin with
Note:
Respect to Ground(1) ............. -0.5V to +VCC +2.0V
(1) Output shorted for no more than one second. No more than
one output shorted at a time.
VCC with Respect to Ground ................ -0.5V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(1) ........................ 100 mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +3.0V to +5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
VIN = GND to Vcc
VIN = GND to Vcc
Min
-2
Typ
Max
10
Units
µA
ILI
Input Leakage Current
Output Leakage Current
ILO
-10
10
µA
f
SCL = 400kHz
VCC = 5.5V
ICC1
ICC2
ISB
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
3
1
mA
mA
µA
f
SCL = 400kHz
VCC = 5.5V
Vcc = 5.5V,
40
VIN = GND or Vcc
2
VIL
Input Low Voltage
Input High Voltage
-0.5
0.3 x Vcc
Vcc + 0.5
V
V
2
VIH
0.7 x Vcc
Output Low Voltage
IOL = 3mA
VCC = 3.0V
VOL
VOH
0.4
V
V
(SDA, RESET)
Output High Voltage
(RESET)
IOH = -0.4mA
VCC = 3.0V
Vcc -
0.75
CAT132x-45
(VCC = 5V)
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
CAT132x-42
(VCC = 5V)
CAT132x-30
(VCC = 3.3V)
VTH
Reset Threshold
V
CAT132x-28
(VCC = 3.3V)
CAT132x-25
(VCC = 3V)
1
VRVALID
Reset Output Valid VCC Voltage
Reset Threshold Hysteresis
1.00
15
V
1
VRT
mV
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. min and V max are reference values only and are not tested.
V
IL
IH
Doc No. 25085, Rev. 00
3
CAT1320, CAT1321
CAPACITANCE
Advance Information
T = 25°C, f = 1.0 MHz, V
A
= 5V
CC
Symbol Test
Test Conditions
VOUT = 0V
Max
8
Units
pF
(1)
COUT
Output Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6
pF
A.C. CHARACTERISTICS
VCC = 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle2
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
Input Filter Spike
Suppression (SDA, SCL)
1
tSP
100
ns
tLOW
tHIGH
Clock Low Period
Clock High Period
1.3
0.6
µs
µs
ns
ns
µs
1
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
300
300
1
tF
tHD;STA
tSU;STA
0.6
0.6
Start Condition Setup Time
(for a Repeated Start)
µs
tHD;DAT
tSU;DAT
tSU;STO
tAA
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
0
ns
ns
µs
ns
ns
100
0.6
900
tDH
50
Time the Bus must be Free Before a
New Transmission Can Start
1
tBUF
1.3
µs
3
tWC
Write Cycle Time (Byte or Page)
5
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
Doc. No. 25085, Rev. 00
4
Advance Information
CAT1320, CAT1321
RESET CIRCUIT A.C. CHARACTERISTICS
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPURST
tRPD
Reset Timeout
Note 2
Note 3
130
200
270
5
ms
µs
VTH to RESET output Delay
tGLITCH
MR Glitch
tMRW
VCC Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
Note 4, 5
Note 5
30
ns
ns
µs
100
Note 5
5
POWER-UP TIMING5,6
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
270
270
ms
ms
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
3. Power-Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
4.
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. and t are the delays required from the time V is stable until the specified memory operation can be initiated.
V
Glitch Reference Voltage = V ; Based on characterization data
THmin
CC
t
PUR
PUW
CC
AC TEST CONDITIONS
Input pulse voltages
0.2VCC to 0.8VCC
10 ns
Input rise and fall times
Input reference voltages
Output reference voltages
0.3VCC, 0.7VCC
0.5VCC
Current Source: IOL = 3mA;
CL = 100pF
Output Load
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
(1)
VZAP
Volts
(1)(2)
ILTH
mA
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V + 1V.
CC
Doc No. 25085, Rev. 00
5
CAT1320, CAT1321
Advance Information
DEVICE OPERATION
Reset Controller Description
When RESET I/O is driven to the active state, the 200
msec timer will begin to time the reset interval. If external
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
The CAT1320/21 precision Reset controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open-
drain RESET/RESET outputs.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
During power-up, the RESET/RESET output remains
active until VCC reaches the VTH threshold and will
continue driving the outputs for approximately 200ms
(tPURST) after reaching VTH. After the tPURST timeout
interval, the device will cease to drive the reset output.
At this point the reset output will be pulled up or down by
their respective pull up/down resistors.
Hardware Data Protection
The CAT1320/21 family has been designed to solve
many of the data corruption issues that have long been
associatedwithserialEEPROMs. Datacorruptionoccurs
when incorrect data is stored in a memory location which
is assumed to hold correct data.
During power-down, the RESET/RESET output will be
active when VCC falls below VTH. The RESET/RESET
output will be valid so long as VCC is >1.0V (VRVALID).
The device is designed to ignore the fast negative going
VCC transient pulses (glitches).
WheneverthedeviceisinaResetcondition,theembedded
EEPROM is disabled for all operations, including write
operations. If the Reset output is active, in progress
communicationstotheEEPROMareabortedandnonew
communications are allowed. In this condition an internal
write cycle to the memory can not be started, but an in
progressinternalnon-volatilememorywritecyclecannot
be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum
value of 2V.
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
t
GLITCH
Figure 1. RESET/RESET Output Timing
V
TH
V
RVALID
t
RPD
t
V
t
PURST
CC
t
RPD
PURST
RESET
RESET
Doc. No. 25085, Rev. 00
6
Advance Information
CAT1320, CAT1321
Figure 2. RESET as Manual Reset Input Operation and Timing
t
MRW
RESET
(Input)
t
PURST
RESET
(Output)
Figure 3. Bus Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Doc No. 25085, Rev. 00
7
CAT1320, CAT1321
Advance Information
EMBEDDED EEPROM OPERATION
SDA when SCL is HIGH. The CAT1320/21 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The CAT1320 and CAT1321 feature a 32kbit
embedded serial EEPROM that supports the I2C Bus
data transmission protocol. This Inter-Integrated
Circuit Bus protocol defines any device that sends
data to the bus to be a transmitter and any device
receiving data to be a receiver. The transfer is
controlled by the Master device which generates the
serial clock and all START and STOP conditions for
bus access. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition.TheMastersendstheaddressoftheparticular
slave device it is requesting. The four most significant
bitsofthe8-bitslaveaddressareprogrammableinmetal
and the default is 1010.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
ReadorWriteoperationistobeperformed.Whenthisbit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT1320/21 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1320/21 then performs a Read or Write operation
depending on the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc. No. 25085, Rev. 00
8
Advance Information
CAT1320, CAT1321
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Byte Write
In the Byte Write mode, the Master device sends the
STARTconditionandtheslaveaddressinformation(with
theR/Wbitsettozero)totheSlavedevice.AftertheSlave
generates an acknowledge, the Master sends two 8-bit
address bytes that are to be written into the address
pointersofthedevice.Afterreceivinganotheracknowledge
fromtheSlave, theMasterdevicetransmitsthedatatobe
writtenintotheaddressedmemorylocation.TheCAT1320/
21 acknowledges once more and the Master generates
the STOP condition. At this time, the device begins an
internalprogrammingcycletonon-volatilememory.While
the cycle is in progress, the device will not respond to any
request from the Master device.
The CAT1320/21 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress.Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
WhentheCAT1320/21beginsaREADmodeittransmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1320/21 will continue to transmit
data.IfnoacknowledgeissentbytheMaster,thedevice
terminates data transmission and waits for a STOP
condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7. Slave Address Bits
Default Configuration
1
0
1
0
A2
A1
A0 R/W
Doc No. 25085, Rev. 00
9
CAT1320, CAT1321
Advance Information
Page Write
The CAT1320/21 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page
writeoperationisinitiatedinthesamemannerasthebyte
write operation, however instead of terminating after the
initialbyteistransmitted,theMasterisallowedtosendup
to additional 63 bytes. After each byte has been
transmitted, the CAT1320/21 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
IftheMastertransmitsmorethan64bytesbeforesending
theSTOPcondition, theaddresscounter‘wrapsaround,’
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1320/21 in a single write cycle.
Figure 8. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
15
8
7
SDA LINE
S
P
***
*
A
C
K
A
C
K
A
C
K
A
C
K
*=Don’t Care Bit
Figure 9. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
DATA n
DATA n+63
15
8
7
SDA LINE
S
P
****
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
*=Don’t Care Bit
Doc. No. 25085, Rev. 00
10
Advance Information
Acknowledge Polling
CAT1320, CAT1321
Read Operations
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issuedtoindicatetheendofthehost’swriteopration, the
CAT1320/21initiatestheinternalwritecycle.ACKpolling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation.Ifthedeviceisstillbusywiththewriteoperation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
The READ operation for the CAT1320/21 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc No. 25085, Rev. 00
11
CAT1320, CAT1321
Advance Information
Immediate/Current Address Read
Sequential Read
The CAT1320 and CAT1321 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=4,095. The counter will wrap around to Zero and
continue to clock out valid data. After the CAT1320 and
CAT1321 receives its slave address information (with
the R/W bit set to one), it issues an acknowledge, then
transmits the 8-bit byte requested. The master device
does not send an acknowledge, but will generate a
STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1320 and CAT1321 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data.TheCAT1320andCAT1321willcontinuetooutput
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1320 and
CAT1321issentsequentiallywiththedatafromaddress
N followed by data from address N+1. The READ
operationaddresscounterincrementsalloftheCAT1320
and CAT1321 address bits so that the entire memory
array can be read during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After the CAT1320 and CAT1321
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1320 and CAT1321 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
SLAVE
ADDRESS
A
DATA
15
8
7
SDA LINE
S
S
P
*
* *
*
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
*=Don’t Care Bit
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 25085, Rev. 00
12
Advance Information
CAT1320, CAT1321
PACKAGE OUTLINES
8-LEAD PDIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
D
0.120 (3.05)
0.150 (3.81)
0.180 (4.57) MAX
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
—
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Dimension D
Pkg
Min
Max
0.400 (10.16)
8L
0.355 (9.02)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
Doc No. 25085, Rev. 00
13
CAT1320, CAT1321
Advance Information
PACKAGE OUTLINES
8-LEAD SOIC (J, W)
0.1497 (3.80) 0.2284 (5.80)
0.1574 (4.00) 0.2440 (6.20)
0.1890 (4.80)
0.1968 (5.00)
0.0532 (1.35)
0.0688 (1.75)
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0.0040 (0.10)
0.0098 (0.25)
0.0099 (0.25)
0.0196 (0.50)
x 46
°
0.0075 (0.19)
0.0098 (0.25)
0 - 8
°
°
0.016 (0.40)
0.050 (1.27)
Dimension D
Min
0.1890(4.80)
Pkg
Max
8L
0.1968(5.00)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc. No. 25085, Rev. 00
14
Advance Information
CAT1320, CAT1321
PACKAGE OUTLINES
8-LEAD TSSOP (U, Y)
Doc No. 25085, Rev. 00
15
CAT1320, CAT1321
Advance Information
PACKAGE OUTLINES
8-PAD TDFN 4.9X3MM PACKAGE (RD2, ZD2)
A
5
8
8
5
B
2.00 + 0.15
0.15
0.20
0.60 + 0.10 (8X)
PIN 1 ID
2x
d
0.15 c
1
4
3.00 + 0.10
(S)
4
1
2x
d
0.15 c
0.30 + 0.05 (8X)
8x
0.65 TYP. (6x)
PIN 1 INDEX AREA
1.95 REF. (2x)
j
0.10m C A B
0.75 + 0.05
f 0.10 c
0.20 REF.
8x
d 0.08 c
C
NOTE:
1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
COPLANARITY SHALL NOT EXCEED 0.08mm.
3. WARPAGE SHALL NOT EXCEED 0.10mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL
CHARACTERISTIC(S).
5. REFER TO JEDEC MO-229, FOOTPRINTS ARE COMPATIBLE TO 8 MSOP.
0.0-0.05
Doc. No. 25085, Rev. 00
16
Advance Information
CAT1320, CAT1321
Ordering Information
Prefix
Device #
1320
Suffix
-30
CAT
J
I
TE13
Optional
Company ID
Temperature Range
I = Industrial (-40˚C to 85˚C)
Tape & Reel
Product
Number
1320: 32K
TE13: 2000/Reel
SOIC: 2000/Reel
TSSOP: 2000/Reel
TDFN: 2000/Reel
1321: 32K
Package
P: PDIP
J: SOIC
U: TSSOP
RD2: 8-pad TDFN (4.9mmx3mm)
L: PDIP (Lead free, Halogen free)
W: SOIC, JEDEC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
ZD2: TDFN 4.9x3mm (Lead free, Halogen free)
ResetThreshold
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
Note:
2
(1) The device used in the above example is a CAT1320JI-30TE13 (Supervisory circuit with I C serial 32k CMOS EEPROM, SOIC, Industrial
Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel).
Doc No. 25085, Rev. 00
17
REVISION HISTORY
Date
Rev.
Reason
1/25/2005
00
Initial issue
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION and SPECIFICALLY DISCLAIMS ANY and ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 25085
Fax: 408.542.1200
Revison:
00
www.catalyst-semiconductor.com
Issue date:
1/25/05
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