CAT140169RWI-G [CATALYST]
IC,SERIAL EEPROM,2KX8,CMOS,SOP,8PIN,PLASTIC;
| 型号： | CAT140169RWI-G |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | IC,SERIAL EEPROM,2KX8,CMOS,SOP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT140xx
Voltage Supervisor with I2C Serial
CMOS EEPROM
FEATURES
DESCRIPTION
Precision Power Supply Voltage Monitor
5V, 3.3V, 3V & 2.5V systems
The CAT140xx (see table below) are memory and
supervisory solutions for microcontroller based systems. A
CMOS serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together. Memory interface is via both the standard
(100kHz) as well as fast (400kHz) I2C protocol.
7 threshold voltage options
Active High or Low Reset
Valid reset guaranteed at VCC = 1 V
Supports Standard and Fast I2C Protocol
The CAT140xx provides a precision VCC sense circuit
with two reset output options: CMOS active low output
or CMOS active high. The RESET output is active
whenever VCC is below the reset threshold or falls
below the reset threshold voltage.
16-Byte Page Write Buffer
Low power CMOS technology
1,000,000 Program/Erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8-pin SOIC package
The power supply monitor and reset circuit protect
system controllers during power up/down and against
brownout conditions. Seven reset threshold voltages
support 5V, 3.3V, 3V and 2.5V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 240ms after the supply
voltage exceeds the reset threshold level.
For Ordering Information details, see page 14.
PIN CONFIGURATION
SOIC (W)
MEMORY SIZE SELECTOR
CAT14016 / 08 / 04 / 02
NC / NC / NC / A
1
2
3
4
8
7
6
5
V
CC
0
Product
14002
14004
14008
14016
Memory density
2-Kbit
NC / NC / A
A
A
V
/
/
RST/RST
SCL
1
1
A
A
2
NC /
/
2
2
4-Kbit
SDA
SS
8-Kbit
16-Kbit
PIN FUNCTION
THRESHOLD SUFFIX SELECTOR
Pin Name
A0, A1, A2
SDA
Function
Nominal Threshold
Voltage
Threshold Suffix
Designation
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Reset Output
4.63V
4.38V
4.00V
3.08V
2.93V
2.63V
2.32V
L
M
J
SCL
¯¯¯¯
RST/RST
VCC
VSS
NC
Power Supply
T
S
R
Z
Ground
No Connect
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1117 Rev. A
CAT140xx
BLOCK DIAGRAM
VCC
SDA
SCL
VOLTAGE
DETECTOR
EEPROM
RST or RST
A0
A1
A2
VSS
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65 to +150
-0.5 to +6.5
°C
V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter
NEND(4) Endurance
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS
CC = +2.5V to +5.5V unless otherwise specified.
V
Limits
Min.
Typ.
Max.
Symbol Parameter
Test Condition
Units
ICC
Supply Current
1
22
Read or Write at 400kHz
mA
10
8
VCC < 5.5V; All I/O Pins at VSS or VCC
ISB
Standby Current
μA
17
VCC < 3.6V; All I/O Pins at VSS or VCC
IL
I/O Pin Leakage
Input Low Voltage
Input High Voltage
2
Pin at GND or VCC
μA
V
VIL
-0.5
VCC x 0.3
VCC + 0.5
VIH
VCC x 0.7
V
VOL
Output Low Voltage
SDA
0.4
V
VCC ≥ 2.5 V, IOL = 3.0 mA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
Doc. No. 1117 Rev. A
2
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT140xx
A.C. CHARACTERISTICS (MEMORY)(1)
CC = 2.5V to 5.5V, TA = -40°C to 85°C, unless otherwise specified.
V
Standard
Fast
Max
Units
Min
Max
Min
Symbol Parameter
FSCL
tHD:STA
tLOW
Clock Frequency
100
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
ns
ns
ms
ms
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
4.7
0
Data In Setup Time
250
100
(2)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
1000
300
300
300
(2)
tF
tSU:STO
tBUF
tAA
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
4
0.6
1.3
4.7
3.5
0.9
tDH
Ti(2)
100
100
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
100
5
100
5
tWR
(2, 3)
tPU
Power-up to Ready Mode
1
1
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
Input Reference Levels
50 ns
≤
0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load
Current Source: IOL = 3 mA; CL = 100 pF
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1117 Rev. A
CAT140xx
ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
VCC = Full range, TA = -40ºC to +85ºC unless otherwise noted. Typical values at TA = +25ºC and VCC = 5V for
L/M/J versions, VCC = 3.3V for T/S versions, VCC = 3V for R version and VCC = 2.5V for Z version.
Symbol
Parameter
Threshold Conditions
Min
Typ
Max Units
4.70
VTH
Reset Threshold Voltage
TA = +25ºC
L
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
4.63
TA = -40ºC to +85ºC
4.75
TA = +25ºC
4.38
4.00
3.08
2.93
2.63
2.32
4.45
M
J
TA = -40ºC to +85ºC
TA = +25ºC
4.50
4.06
TA = -40ºC to +85ºC
TA = +25ºC
4.10
3.11
V
T
S
R
Z
TA = -40ºC to +85ºC
TA = +25ºC
3.15
2.96
3.00
2.66
2.70
2.35
2.38
TA = -40ºC to +85ºC
TA = +25ºC
TA = -40ºC to +85ºC
TA = +25ºC
TA = -40ºC to +85ºC
Symbol Parameter
Reset Threshold Tempco
VCC to Reset Delay(2)
Conditions
Min
Typ(1) Max Units
30
20
ppm/ºC
µs
tRPD
VCC = VTH to (VTH -100mV)
TA = -40ºC to +85ºC
tPURST Reset Active Timeout Period
140
240
460
0.3
0.4
0.3
ms
V
¯¯¯¯¯¯
RESET Output Voltage Low
VCC = VTH min, ISINK = 1.2 mA
R/S/T/Z
(Push-pull, active LOW,
CAT140xx9)
VCC = VTH min, ISINK = 3.2 mA
J/L/M
VOL
VCC > 1.0V, ISINK = 50µA
VCC = VTH max, ISOURCE = -500µA
R/S/T/Z
0.8VCC
¯¯¯¯¯¯
(Push-pull, active LOW,
CAT140xx9)
RESET Output Voltage High
VOH
V
VCC = VTH max, ISOURCE = -800µA
J/L/M
VCC - 1.5
VCC > VTH max, ISINK = 1.2mA
R/S/T/Z
RESET Output Voltage Low
0.3
0.4
VOL
V
V
(Push-pull, active HIGH,
CAT140xx1)
VCC > VTH max, ISINK = 3.2mA
J/L/M
RESET Output Voltage High
1.8V < VCC ≤ VTH min,
ISOURCE = -150µA
VOH
0.8VCC
(Push-pull, active HIGH,
CAT140xx1)
Notes:
(1) Production testing done at TA = +25ºC; limits over temperature guaranteed by design only.
(2) RESET output for the CAT140xx9; RESET output for the CAT140xx1.
Doc. No. 1117 Rev. A
4
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT140xx
and remains asserted for at least 140ms (tPURST) after
the power supply voltage has risen above the threshold.
Reset output timing is shown in Figure 1.
PIN DESCRIPTION
¯¯¯¯¯¯
RESET/RESET : RESET OUTPUT
This output is available in two versions: CMOS
Active Low (CAT140xx9) and CMOS Active High
(CAT140xx1). Both versions are push-pull outputs
for high efficiency.
The CAT140xx devices protect μPs against brownout
failure. Short duration VCC transients of 4μsec or less
and 100mV amplitude typically do not generate a Reset
pulse.
SDA: SERIAL DATA ADDRESS
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode,
this pin is open drain. Data is acquired on the
positive edge, and is delivered on the negative edge
of SCL.
Figure 2 shows the maximum pulse duration of negative-
going VCC transients that do not cause a reset condition.
As the amplitude of the transient goes further below the
threshold (increasing VTH - VCC), the maximum pulse
duration decreases. In this test, the VCC starts from
an initial voltage of 0.5V above the threshold and
drops below it by the amplitude of the overdrive voltage
(VTH - VCC).
SCL: SERIAL CLOCK
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
A0, A1, A2: Device Address Inputs
T
AMB
= 25ºC
The Address inputs set the device address when
cascading multiple devices. When not driven, these
pins are pulled LOW internally.
CAT140xxZ
DEVICE OPERATION
The CAT140xx products combine the accurate
voltage monitoring capabilities of a standalone
voltage supervisor with the high quality and reliability
of standard EEPROMs from Catalyst Semiconductor.
CAT140xxM
RESET CONTROLLER DESCRIPTION
RESET OVERDRIVE V - V
[mV]
TH
CC
The reset signal is asserted LOW for the CAT140xx9
and HIGH for the CAT140xx1 when the power
supply voltage falls below the threshold trip voltage
Figure 2. Maximum Transient Duration Without
Causing a Reset Pulse vs. Overdrive Voltage
VTH
VCC
V
RVALID
tRPD
tPURST
tRPD
tPURST
RESET
RESET
CAT140xx9
CAT140xx1
Figure 1. RESET Output Timing
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1117 Rev. A
CAT140xx
EMBEDDED EEPROM OPERATION
STOP
The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while
SCL is HIGH. The STOP starts the internal Write cycle
(when following a Write command) or sends the
Slave into standby mode (when following a Read
command).
The CAT140xx supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and
a device receiving data as a receiver. Data flow is
controlled by a Master device, which generates the
serial clock and all START and STOP conditions. The
CAT140xx acts as a Slave device. Master and Slave
alternate as either transmitter or receiver.
Device Addressing
The Master initiates data transfer by creating a
START condition on the bus. The Master then
broadcasts an 8-bit serial Slave address. For normal
Read/Write operations, the first 4 bits of the Slave
address are fixed at 1010 (Ah). The next 3 bits are
used as programmable address bits when cascading
multiple devices and/or as internal address bits. The
last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed.
The 3 address space extension bits are assigned as
illustrated in Figure 4. A2, A1 and A0 must match the
state of the external address pins, and a10, a9 and a8
are internal address bits.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA.
The two wires are connected to the VCC supply via
pull-up resistors. Master and Slave devices connect to
the 2-wire bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 3). The START condition precedes
all commands. It consists of a HIGH to LOW transition
on SDA while SCL is HIGH. The START acts as a
‘wake-up’ call to all receivers. Absent a START, a
Slave will not respond to commands. The STOP
condition completes all commands. It consists of a
LOW to HIGH transition on SDA while SCL is HIGH.
Acknowledge
After processing the Slave address, the Slave
responds with an acknowledge (ACK) by pulling down
the SDA line during the 9th clock cycle (Figure 5). The
Slave will also acknowledge the address byte and
every data byte presented in Write mode. In Read
mode the Slave shifts out a data byte, and then
releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave
will continue transmitting. The Master terminates the
session by not acknowledging the last data byte
(NoACK) and by issuing a STOP condition. Bus timing
is illustrated in Figure 6.
START
The START condition precedes all commands.
It consists of a HIGH to LOW transition on SDA while
SCL is HIGH. The START acts as a ‘wake-up’ call to
all receivers. Absent a START, a Slave will not
respond to commands.
Doc. No. 1117 Rev. A
6
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT140xx
Figure 3. START/STOP Conditions
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 4. Slave Address Bits
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A
A
A
A
A
A
R/W
R/W
R/W
R/W
CAT14002
2
2
2
1
1
9
9
0
8
8
8
a
a
a
CAT14004
CAT14008
CAT14016
a
a
a
10
Figure 5. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
SU:DAT
)
START
ACK DELAY (≤ t
)
AA
Figure 6. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
t
DH
AA
SDA OUT
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1117 Rev. A
CAT140xx
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set
to zero to the Slave. After the Slave generates an
acknowledge, the Master sends the byte address that
is to be written into the address pointer of the
CAT140xx. After receiving another acknowledge from
the Slave, the Master transmits the data byte to be
written into the addressed memory location. The
CAT140xx device will acknowledge the data byte and
the Master generates the STOP condition, at which
time the device begins its internal Write cycle to
nonvolatile memory (Figure 7). While this internal
cycle is in progress (tWR), the SDA output will be tri-
stated and the CAT140xx will not respond to any
request from the Master device (Figure 8).
Page Write
The CAT140xx writes up to 16 bytes of data in a
single write cycle, using the Page Write operation
(Figure 9). The Page Write operation is initiated in the
same manner as the Byte Write operation, however
instead of terminating after the data byte is
transmitted, the Master is allowed to send up to fifteen
additional bytes. After each byte has been transmitted
the CAT140xx will respond with an acknowledge and
internally increments the four low order address bits.
The high order bits that define the page address
remain unchanged. If the Master transmits more than
sixteen bytes prior to sending the STOP condition, the
address counter ‘wraps around’ to the beginning of
page and previously transmitted data will be
overwritten. Once all sixteen bytes are received and
the STOP condition has been sent by the Master, the
internal Write cycle begins. At this point all received
data is written to the CAT140xx in a single write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used
to take advantage of the typical write cycle time.
Once the stop condition is issued to indicate the end
of the host’s write operation, the CAT140xx initiates
the internal write cycle. The ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the CAT140xx is still busy with the write
operation, NoACK will be returned. If the CAT140xx
has completed the internal write operation, an ACK
will be returned and the host can then proceed with
the next read or write operation.
Doc. No. 1117 Rev. A
8
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT140xx
Figure 7. Byte Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
O
P
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
a
a
7⎟ 0
d
d
7÷ 0
S
P
A
C
K
A
C
K
A
C
K
SLAVE
Figure 8. Write Cycle Timing
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 9. Page Write Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
ADDRESS
BYTE
SLAVE
ADDRESS
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
n = 1
P ≤ 15
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1117 Rev. A
CAT140xx
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set
to ‘1’, the CAT140xx will interpret this as a request for
data residing at the current byte address in memory.
The CAT140xx will acknowledge the Slave address,
will immediately shift out the data residing at the
current address, and will then wait for the Master to
respond. If the Master does not acknowledge the data
(NoACK) and then follows up with a STOP condition
(Figure 10), the CAT140xx returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT140xx acknowledges the byte
address, the Master device resends the START
condition and the slave address, this time with the R/W
bit set to one. The CAT140xx then responds with its
acknowledge and sends the requested data byte. The
Master device does not acknowledge the data (NoACK)
but will generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges
the 1st data byte, then the CAT140xx will continue
transmitting data residing at subsequent locations until
the Master responds with a NoACK, followed by a
STOP (Figure 12). In contrast to Page Write, during
Sequential Read the address count will automatically
increment to and then wrap-around at end of memory
(rather than end of page).
POWER-ON RESET (POR)
Each CAT140xx incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
A CAT140xx device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the
POR trigger level. This bi-directional POR feature
protects the device against ‘brown-out’ failure follo–
wing a temporary loss of power.
Delivery State
The CAT140xx is shipped erased, i.e., all bytes are FFh.
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
10
Doc. No. 1117 Rev. A
CAT140xx
Figure 10. Immediate Read Sequence and Timing
N
O
S
T
BUS ACTIVITY:
S
A
R
T
A T
C O
K P
SLAVE
ADDRESS
MASTER
SLAVE
S
P
A
C
K
DATA
BYTE
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 11. Selective Read Sequence
N
S
T
A
R
T
S
T
A
R
T
O
BUS ACTIVITY:
MASTER
S
A T
C O
K P
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 12. Sequential Read Sequence
N
O
S
T
O
P
BUS ACTIVITY:
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
MASTER
SLAVE
ADDRESS
P
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1117 Rev. A
CAT140xx
PACKAGE OUTLINES
8-LEAD 150 MIL SOIC (W)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS-012 dimensions.
Doc. No. 1117 Rev. A
12
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT140xx
ORDERING INFORMATION
Prefix
Device # Suffix
14002
CAT
9
S
W
I
-
G
T3
Lead Finish
G: NiPdAu (PPF)
Company ID
Temperature Range
Tape & Reel
I = Industrial (-40ºC to 85ºC)
T: Tape & Reel
3: 3000 units / Reel
Product Type with
Memory Density
02 – 2K-bits
04 – 4K-bits
08 – 8K-bits
Package
W: SOIC
16 – 16K-bits
Reset Threshold Voltage
L: 4.50V – 4.75V
M: 4.25V – 4.50V
J: 3.89V – 4.10V
T: 3.00V – 3.15V
S: 2.85V – 3.00V
R: 2.55V – 2.70V
Z: 2.25V – 2.38V
Supervisor Output Type
9: CMOS Active Low
1: CMOS Active High
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames.
(3) The device used in the above example is a CAT140029SWI-GT3 (2Kb EEPROM, with Active Low CMOS output, with a reset threshold between
2.85V - 3.00V, in an SOIC, Industrial Temperature, NiPdAu, Tape and Reel.
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 1117 Rev. A
REVISION HISTORY
Date
Rev. Reason
Initial Issue
11/09/06
A
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Document No: 1117
Revision:
A
Issue date:
11/09/06
相关型号：
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