CAT24AC128GXE-REV-A [CATALYST]
EEPROM, 16KX8, Serial, CMOS, PDSO8, 0.210 INCH, LEAD FREE AND HALOGEN FREE, EIAJ, SOIC-8;
| 型号： | CAT24AC128GXE-REV-A |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 16KX8, Serial, CMOS, PDSO8, 0.210 INCH, LEAD FREE AND HALOGEN FREE, EIAJ, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总11页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT24AC128
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins
E TM
R
FEATURES
I 400kHz (2.5V) and 100kHz (1.8V) I2C bus
I Commercial, industrial and extended
compatibility
automotive temperature ranges
I 1.8 to 5.5 volt operation
I Low power CMOS technology
I Write protect feature
– Entire array protected when WP at VIH
I 1,000,000 program/erase cycles
I 100 year data retention
I Schmitt trigger filtered inputs for noise
suppression
I 64-Byte page write buffer
I 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or
14-pin TSSOP
I Self-timed write cycle with auto-clear
DESCRIPTION
The CAT24AC128 is a 128kbit Serial CMOS EEPROM
internally organized as 16,384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reducesdevicepowerrequirements. TheCAT24AC128
featuresa64-bytepagewritebuffer.Thedeviceoperates
via the I2C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three
device address inputs allows up to 8 devices to share a
common 2-wire I2C bus.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, K, W, X)
EXTERNAL LOAD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
CC
WP
A0
A1
A2
A0
A1
CC
SENSE AMPS
SHIFT REGISTERS
D
OUT
WP
ACK
A2
SCL
SDA
SCL
SDA
V
V
CC
SS
V
V
SS
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
TSSOP Package (U14, Y14)
512
1
2
3
4
5
6
7
14
13
12
11
10
9
A0
V
WP
NC
NC
NC
CC
START/STOP
SDA
A1
NC
NC
NC
A2
LOGIC
E2PROM
256X512
XDEC
256
SCL
SDA
V
8
SS
CONTROL
LOGIC
WP
PIN FUNCTIONS
DATA IN STORAGE
Pin Name
Function
SDA
SCL
WP
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
Write Protect
SCL
STATE COUNTERS
VCC
+1.8V to +5.5V Power Supply
Ground
SLAVE
ADDRESS
COMPARATORS
A0
A1
A2
VSS
A0 - A2
Device Address Inputs
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Doc. No. 1028, Rev. I
1
Characteristics subject to change without notice
CAT24AC128
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Typ.
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
Power Supply Current - Read
f
= 100 KHz
1
mA
CC1
SCL
V
= 5V
CC
I
Power Supply Current - Write
Standby Current
f
= 100 KHz
3
1
mA
CC2
SCL
V
= 5V
CC
(5)
I
V
V
= GND or V
µA
SB
IN
CC
V
= 5V
CC
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
= GND to V
3
3
µA
µA
LI
IN
CC
I
V
= GND to V
LO
OUT CC
V
IL
–1
x 0.7
V
x 0.3
V
V
V
V
CC
V
Input High Voltage
V
V
+ 0.5
CC
IH
CC
V
V
Output Low Voltage (V
Output Low Voltage (V
= +3.0V)
= +1.8V)
I
I
= 3.0 mA
= 1.5 mA
0.4
OL1
CC
OL
0.5
OL2
CC
OL
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP, A0, A1, A2)
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max
8
Units
pF
(3)
CI/O
(3)
CIN
6
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Maximum standby current (I ) = 10µA for the Extended Automotive temperature range.
SB
Doc. No. 1028, Rev. I
2
CAT24AC128
A.C. CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified
V
CC
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC = 1.8 V - 5.5 V
VCC = 2.5 V - 5.5 V
Min
Max
100
3.5
Min
Max
400
0.9
Units
kHz
µs
FSCL
tAA
Clock Frequency
SCL Low to SDA Data Out
and ACK Out
0.1
4.7
0.05
1.2
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.0
0.6
1.2
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
ms
ns
Data In Setup Time
100
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.0
0.3
(1)
tF
300
300
tSU:STO
tDH
4.7
0.6
50
100
tWR
Write Cycle Time
5
5
tSP
Input Suppression (SDA, SCL)
100
100
(1)(2)
Power-Up Timing
Symbol
Parameter
Min
Typ
Max
Units
ms
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24AC128 supports the I2C Bus data
STOP conditions for bus access. The CAT24AC128
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
operates as a Slave device. Both the Master device and
Slavedevicecanoperateaseithertransmitterorreceiver,
but the Master device controls which mode is activated.
Doc. No. 1028, Rev. I
3
CAT24AC128
PIN DESCRIPTIONS
I2C BUS PROTOCOL
SCL: Serial Clock
The features of the I2C bus protocol are defined as
follows:
The serial clock input clocks all data transferred into or
out of the device.
(1) Data transfer may be initiated only when the bus is
not busy.
SDA: Serial Data/Address
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
START Condition
WP: Write Protect
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24AC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1, A2: Device Address Inputs
STOP Condition
These inputs set the device address when cascading
multiple devices. When these pins are left floating the
default values are zeroes. A maximum of eight devices
can be cascaded.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1028, Rev. I
4
CAT24AC128
DEVICE ADDRESSING
WhentheCAT24AC128beginsaREADmodeittransmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge,theCAT24AC128willcontinuetotransmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three significant bits (A2, A1, A0)
are the device address bits and define which device the
master is accessing. Up to eight CAT24AC128 devices
may be individually addressed by the system. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24AC128. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memorylocation.TheCAT24AC128acknowledgesonce
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
After the Master sends a START condition and the slave
address byte, the CAT24AC128 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24AC128 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Page Write
The CAT24AC128 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
The CAT24AC128 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
R/W
A0
*A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3).
Doc. No. 1028, Rev. I
5
CAT24AC128
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24AC128
will accept both slave and byte addresses, but the
memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24AC128 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain
unchanged.
IftheMastertransmitsmorethan64bytesbeforesending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
READ OPERATIONS
The READ operation for the CAT24AC128 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24AC128 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24AC128 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24AC128 is still busy with the
write operation, no ACK will be returned. If
CAT24AC128 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Immediate/Current Address Read
The CAT24AC128’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
accessdatafromaddressN+1.IfN=E(whereE=16383),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24AC128
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
WRITE PROTECTION
Selective/Random Address Read
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
Selective/Random READ operations allow the Master
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
15
8
7
SDA LINE
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
DATA n
DATA n+63
15
8
7
SDA LINE
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Doc. No. 1028, Rev. I
6
CAT24AC128
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After CAT24AC128 acknowledges, the
MasterdevicesendstheSTARTconditionandtheslave
address again, this time with the R/W bit set to one. The
CAT24AC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
data. The CAT24AC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
withanacknowledge,thussendingtheSTOPcondition.
The data being transmitted from CAT24AC128 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1.TheREADoperationaddress
counterincrementsalloftheCAT24AC128addressbits
so that the entire memory array can be read during one
operation. If more than E (where E=16383) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. AftertheCAT24AC128sendstheinitial8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
Figure 8. Current Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
24AC128 F08
Figure 9. Random Address Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
SLAVE
ADDRESS
A
15
–A
A –A
DATA
8
7
0
SDA LINE
S
S
P
* *
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
*=Don't Care Bit
Doc. No. 1028, Rev. I
7
CAT24AC128
Figure 10. Sequential Current Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 11. Sequential Random Address Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A
SLAVE
ADDRESS
A
A
–A
0
DATA n
DATA n+1
DATA n+2
DATA n+x
15
8
7
SDA LINE
S
S
P
* *
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
ORDERING INFORMATION
24AC128
Rev A(2)
Die Revision
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
L: PDIP (Lead-free, Halogen-free)
X: SOIC, EIAJ (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a CAT24AC128KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt
Operating Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additional
information, please contact your Catalyst sales office.
Doc. No. 1028, Rev. I
8
CAT24AC128
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
0.355 (9.02)
0.400 (10.16)
0.120 (3.05)
0.180 (4.57) MAX
0.150 (3.81)
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
8-LEAD 150 MIL WIDE SOIC (J, W)
0.1497 (3.80) 0.2284 (5.80)
0.1574 (4.00) 0.2440 (6.20)
0.1890 (4.80)
0.1968 (5.00)
0.0099 (0.25)
0.0196 (0.50)
X 45
0.0075 (0.19)
0.0098 (0.25)
0.0532 (1.35)
0.0688 (1.75)
0 —8
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0.0040 (0.10)
0.0098 (0.25)
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
Doc. No. 1028, Rev. I
9
CAT24AC128
8-LEAD 210 MIL WIDE SOIC (K, X)
0.205 (5.20)
0.213 (5.40)
0.303 (7.70)
0.318 (8.10)
0.0267 (0.68)
0.0303 (0.77)
0.205 (5.15)
0.210 (5.35)
0.008 (0.20)
0.080 (2.03)
MAX
4 REF
0.046 (1.17)
0.054 (1.37)
0.025 (0.65)
0.0137 (0.35)
0.0177 (0.45)
Note:
1. All linear dimensions are in inches and parenthetically in millimeters.
14-LEAD TSSOP (U14, Y14)
-D-
8
14
7.72 TYP
4.16 TYP
6.4
+
4.4 0.1
-B-
(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
0.2 C B A
ALL LEAD TIPS
1
7
PIN #1 IDENT.
SEE DETAIL A
1.1 MAX TYP
0.1
C
ALL LEAD TIPS
0.09 - 0.20 TYP
(0.9)
-C-
+
0.10 0.05 TYP
0.65 TYP
GAGE PLANE
0.25
0.19 - 0.30 TYP
0.3 M
A B S C S
0o- 8o
Dimension D
0.6+0.1
SEATING PLANE
Pkg
14
Min
4.9
Max
5.1
DETAIL A
Doc. No. 1028, Rev. I
10
REVISION HISTORY
Date
Rev.
Reason
07/7/2004
G
Added Die Revision to Ordering Information
Started revision history
07/27/2004
06/23/2005
H
I
Updated DC Operating Characteristics table and notes
Update Features
Update Pin Functions
Update Reliability Characteristics
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update Read Operations
Update Figures 8, 9, 10
Add Figure 11
Update Ordering Information
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Phone: 408.542.1000
Publication #: 1028
Fax: 408.542.1200
Revison:
I
www.catalyst-semiconductor.com
Issue date:
06/23/05
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