CAT24C00YE-TE13REV-B [CATALYST]
16X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, LEAD FREE AND HALOGEN FREE, TSSOP-8;
| 型号： | CAT24C00YE-TE13REV-B |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 16X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, LEAD FREE AND HALOGEN FREE, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总10页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C00
128-Bit Serial EEPROM
FEATURES
I 400 kHz I2C bus compatible*
I 1.8 to 5.5 volt operation
I 1,000,000 Program/erase cycles
I 100 year data retention
I Low power CMOS technology
I Self-timed write cycle with auto-clear
I 8-pin DIP, 8-pin SOIC, 8 pin TSSOP and SOT-23
I Industrial and Extended Temperature Ranges
DESCRIPTION
devicepowerrequirements. Thedeviceoperatesviathe
I2C bus serial interface and is available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and 5-pin SOT-23.
The CAT24C00 is a 128-bit Serial CMOS EEPROM
internallyorganizedas16wordsof8bitseach.Catalyst’s
advanced CMOS technology substantially reduces
PIN CONFIGURATION
DIP Package (P, L, GL)
BLOCK DIAGRAM
SOIC Package (J, W, GW)
EXTERNAL LOAD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
NC
NC
NC
V
CC
NC
NC
NC
NC
V
CC
NC
SENSE AMPS
SHIFT REGISTERS
D
OUT
ACK
SCL
SDA
SCL
SDA
V
V
V
CC
SS
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
V
SS
SOT-23 (TP, TB, GTB)
TSSOP Package (U, Y, GY)
START/STOP
SDA
LOGIC
1
2
3
4
8
7
6
5
1
2
3
5
4
V
CC
SCL
NC
NC
NC
V
CC
NC
V
SS
SCL
SDA
NC
SDA
E2PROM
XDEC
V
SS
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
SDA
SCL
NC
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
No Connect
SCL
STATE COUNTERS
VCC
VSS
1.8 V to 5.5 V Power Supply
Ground
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
1
CAT24C00
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ............–2.0 V to VCC + 2.0 V
VCC with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current(2) ....................... 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Typ.
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
= 1.8 V to 5.5 V, unless otherwise specified.
CC
Symbol
Parameter
Power Supply Current
Standby Current (VCC = 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Test Conditions
fSCL = 400 kHz
Min
Typ
Max
2
Units
mA
µA
ICC
(5)
ISB
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
1
ILI
10
10
µA
ILO
VIL
VIH
µA
–1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
Input High Voltage
VCC x 0.7
VOL1 Output Low Voltage (VCC = 3.0 V)
VOL2 Output Low Voltage (VCC = 1.8 V)
IOL = 3 mA
IOL = 1.5 mA
0.5
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5 V
A
CC
Symbol
Parameter
Test Conditions
VI/O = 0 V
VIN = 0 V
Min
Typ
Max
Units
pF
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
8
6
(3)
CIN
pF
Note:
(1) The minimum DC input voltage is – 0.5 V. During transitions, inputs may undershoot to – 2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from – 1 V to V + 1 V.
CC
(5) Maximum standby current (I ) = 10µA for the Extended Automotive temperature range.
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
2
CAT24C00
A.C. CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 6.0 V
2.5 V - 6.0 V
Min
Max
Min
Max
400
100
Units
kHz
ns
FSCL
TI(1)
Clock Frequency
100
100
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
4.7
4
0.6
1.2
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Min
Min
Typ
Max
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Write Cycle Limits
Symbol
Parameter
Typ
Max
Units
tWR
Write Cycle Time
5
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
3
CAT24C00
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The CAT24C00 bidirectional serial data/address pin is
usedtotransferdataintoandoutofthedevice. TheSDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
The CAT24C00 supports the I2C Bus data transmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24C00 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
I2C BUS PROTOCOL
ThefollowingdefinesthefeaturesoftheI2Cbusprotocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24C00 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
AA
DH
SDA OUT
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
4
CAT24C00
START Condition
The CAT24C00 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C00 monitors the
SDA and SCL lines and will not respond until this
condition is met.
When the CAT24C00 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge,
the CAT24C00 will continue to transmit data. If no
acknowledgeissentbytheMaster,thedeviceterminates
data transmission and waits for a STOP condition.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
WRITE OPERATION
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24C00 (see Fig. 5). The next three
significant bits are "don't care" bits. The last bit of the
slaveaddressspecifieswhetheraReadorWriteoperation
is to be performed. When this bit is set to 1, a Read
operationisselected,andwhensetto0,aWriteoperation
is selected.
Byte Write
In the Write mode, the Master device sends the START
condition and the slave address information (with the R/
W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends the byte
address that is to be written into the address pointer of
the CAT24C00. After receiving another acknowledge
from the Slave, the Master device transmits the data
byte to be written into the addressed memory location.
The CAT24C00 acknowledges once more and the
MastergeneratestheSTOPcondition, atwhichtimethe
device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request
from the Master device.
After the Master sends a START condition and the slave
address byte, the CAT24C00 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24C00 then performs a Read or Write operation
depending on the state of the R/W bit.
After a write command, the internal address counter
will continue to point to the same address location
that was just written. If a stop bit is transmitted to the
device at any point in the write sequence before the
entire sequence is complete, then the command will
abort and no data will be written. If more than eight
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
5
CAT24C00
Figure 5. Slave Address Bits
CAT24C00
1
0
1
0
X
X
X
R/W
bits are transmitted before the stop bit is sent, then
the device will clear the previously loaded byte and
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24C00 acknowledges the word
address,theMasterdeviceresendstheSTARTcondition
and the slave address, this time with the R/W bit is set to
one.TheCAT24C00thenrespondswithitsacknowledge
and sends the 8-bit byte requested. To end the Read
Operation the master device does not send an
acknowledge but will generate a STOP condition.
begin loading the data buffer again. If more than one
data byte is transmitted to the device and a stop bit
is sent before a full eight bits of data have been
transmitted, then the write command will abort and
no data will be written.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT24C00 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24C00 is still busy with
the write operation, no ACK will be returned. If the
CAT24C00 has completed the write operation, an ACK
will be returned and the host can then proceed with the
Sequential Read
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective READ
operations. After the CAT24C00 sends initial 8-bit byte
requested, the Master will respond with an acknowledge
which tells the device it requires more data. The
CAT24C00 will continue to output an 8-bit byte for each
acknowledge sent by the Master. The operation is
terminated when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
next read or write operation.
READ OPERATIONS
TheREADoperationfortheCAT24C00isinitiatedinthe
same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
The data being transmitted from the CAT24C00 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1. TheREADoperationaddress
counter increments all of the CAT24C00 address bits so
that the entire memory array can be read during one
operation. Ifmorethan16bytesarereadout, thecounter
will “wrap around” and continue to clock out data bytes.
Immediate Address Read
The device’s address counter contains the address of
the last byte accessed, incremented by one. In other
words, if the last READ access was to address N, the
READ immediately following would access data from
addressN+1.IfN=15,thenthecounterwill'wraparound'
to address 0 and continue to clock out data.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
6
CAT24C00
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
SLAVE
ADDRESS
BYTE
ADDRESS
MASTER
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
8
9
SCL
8TH BIT
SDA
DATA OUT
NO ACK
STOP
Figure 8. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 9. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
7
CAT24C00
ORDERING INFORMATION
Prefix
Device #
24C00
Suffix
(2)
Rev B
X
TE13
J
I
CAT
Temperature Range
I = Industrial (-40°C to 85°C)
E = Extended (-40°C to 125°C)
Product Number
24C00: 128 Bit
Tape & Reel
Optional
Company ID
Operating Voltage
Blank:
Package
Die Revision
1.8 V - 5.5 V
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
TP: SOT23
L : PDIP (Lead free, Halogen free)
TB: SOT23 (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GTB: SOT23 (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a CAT24C00JI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWB). For additional
information, please contact your Catalyst sales office.
© 2005 by Catalyst Semiconductor, Inc.
Doc. No. 1027, Rev. O
8
Characteristics subject to change without notice
CAT24C00
REVISION HISTORY
Date
Rev.
Reason
9/24/2003
H
Eliminated commercial temperature range class
Updated marking
10/30/2003
12/9/2003
12/23/2003
I
Eliminated automotive temperature reange
Changed Industrial temp range designation from "Blank" to "I"
J
K
Eliminatd Commercial and Automotive temp ranges from Features on
front page of data sheet
12/29/2003
L
Moved DC Operating Characteristics typ numbers for VOL1 and VOL2 to
max column
Changed 1.8V to 1.8V - 6.0V for AC Characteristics
Changed 4.5V - 5.5V to 2.5V - 6.0V for AC Characteristics
Added Die Revision to Ordering Information
Updated DC Operating Characteristics chart and notes
Upate Rekiability Characteristics table
7/7/2004
M
N
O
7/27/2004
07/12/2005
Update Ordering Information
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1027, Rev. O
9
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AE2 ™
MiniPot™
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
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Corporate Headquarters
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Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1027
Fax: 408.542.1200
Revison:
O
www.caalyst-semiconductor.com
Issue date:
7/12/05
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