CAT24C128ZIT3 [CATALYST]
128-Kb I2C CMOS Serial EEPROM; 128 KB I2C CMOS串行EEPROM
| 型号： | CAT24C128ZIT3 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 128-Kb I2C CMOS Serial EEPROM |
| 文件： | 总18页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C128
128-Kb I2C CMOS Serial EEPROM
FEATURES
DEVICE DESCRIPTION
■ Supports Standard and Fast I2C Protocol
■ 1.8V to 5.5V Supply Voltage Range
■ 64-Byte Page Write Buffer
The CAT24C128 is a 128-Kb Serial CMOS EEPROM,
internally organized as 16,384 words of 8 bits each.
It features a 64-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
■ Hardware Write Protection for entire memory
■ Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory).
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Industrial and Extended temperature range
■ RoHS-compliant 8-lead PDIP, SOIC, TSSOP and
UDFN packages
For additional packages and Ordering
Information details, see page 15.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (W)
TSSOP (Y)
UDFN (HU3)
V
CC
A
1
8
V
CC
0
SCL
A
2
3
4
7
6
5
WP
1
2
A
SCL
SDA
V
SS
A , A , A
CAT24C128
SDA
2
1
0
For the location of Pin 1, please consult the
corresponding package drawing.
WP
PIN FUNCTIONS
V
SS
A0, A1, A2
SDA
SCL
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
WP
VCC
VSS
Ground
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
1
CAT24C128
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
(4)
NEND
TDR
Endurance
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to +125°C, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
Units
ICCR
ICCW
Read Current
Write Current
Read, fSCL = 400kHz
Write, fSCL = 400kHz
1
mA
mA
3
TA = -40°C to +85°C
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
1
ISB
Standby Current
I/O Pin Leakage
All I/O Pins at GND or VCC
Pin at GND or VCC
μA
μA
2
1
2
IL
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
VCC x 0.3
V
V
V
V
VCC x 0.7 VCC + 0.5
VOL1
VOL2
Output Low Voltage VCC < 2.5 V, IOL = 3.0mA
Output Low Voltage VCC < 2.5 V, IOL = 1.0mA
0.4
0.2
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to +125°C, unless otherwise specified.
Symbol Parameter
Conditions
VIN = 0 V
VIN = 0 V
VIN < VIH
VIN > VIH
Max
8
Units
(3)
CIN
SDA I/O Pin Capacitance
pF
pF
μA
μA
(3)
CIN
IWP
Input Capacitance (other pins)
WP Input Current
6
(5)
200
1
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
© Catalyst Semiconductor, Inc.
Doc. No. MD-1103, Rev. J
2
Characteristics subject to change without notice
CAT24C128
A.C. CHARACTERISTICS(1)
VCC = 1.8 V to 5.5 V, TA = -40°C to +125°C.
Standard
Fast
Symbol
Parameter
Min
Max
Min
Max
Units
FSCL
Clock Frequency
100
400
kHz
tHD:STA
tLOW
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
ns
ns
μs
μs
ms
ms
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
4.7
0
Data Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to SDA Data Out
Data Out Hold Time
1000
300
300
300
(2)
tF
tSU:STO
tBUF
4
0.6
1.3
4.7
tAA
3.5
0.9
tDH
100
100
Ti(2)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
tSU:WP
tHD:WP
tWR
0
0
WP Hold Time
2.5
2.5
Write Cycle Time
5
1
5
1
(2, 3)
tPU
Power-up to Ready Mode
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this paramete.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
≤ 50 ns
Input Rise and Fall Times
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
3
CAT24C128
I2C BUS PROTOCOL
POWER-ON RESET (POR)
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDAline to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
The CAT24C128 incorporates Power-On Reset
(POR) circuitry which protects the device against
powering up in the wrong state.
The CAT24C128 will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDAwhile SCLis HIGH. The STARTacts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
PIN DESCRIPTION
SCL:The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmitsdatastoredinEEPROM.Intransmitmode,this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices and must match the
state of the external address pins. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is
to be performed.
A0, A1 and A2: The Address pins accept the device
address. When not driven, these pins are pulled LOW
internally.
WP: The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Acknowledge
FUNCTIONAL DESCRIPTION
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge all address bytes and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle. As long as the Master acknowl-
edges the data, the Slave will continue transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by issuing a STOP
condition. Bus timing is illustrated in Figure 4.
The CAT24C128 supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
devicereceivingdataasareceiver.Dataflowiscontrolled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C128
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver. Up to 8 devices may be
connected to the bus as determined by the device ad-
dress inputs A0, A1, and A2.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
4
CAT24C128
Figure 1. START/STOP Conditions
SCL
SDA
START
STOP
CONDITION
CONDITION
Figure 2. Slave Address Bits
DEVICE ADDRESS
1
0
1
0
A
A
A
0
R/W
2
1
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
SU:DAT
t
HD:STA
SU:STO
SDA IN
t
BUF
t
t
AA
DH
SDA OUT
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
5
CAT24C128
WRITE OPERATIONS
Hardware Write Protection
Byte Write
With the WP pin held HIGH, the entire memory
is protected against Write operations. If the WP
pin is left floating or is grounded, it has no im-
pact on the operation of the CAT24C128. The
state of the WP pin is strobed on the last falling
edge of SCL immediately preceding the first data byte
(Figure 8). If the WP pin is HIGH during the strobe in-
terval, the CAT24C128 will not acknowledge the data
byte and the Write request will be rejected.
Upon receiving a Slave address with the R/W bit set
to ‘0’, the CAT24C128 will interpret the next two bytes
as address bytes These bytes are used to initialize the
internal address counter; the 2 most significant bits are
‘don’tcare’,thenext8pointtooneof256availablepages
and the last 6 point to a location within a 64 byte page.
Abyte following the address bytes will be interpreted as
data. The data will be loaded into the Page Write Buffer
and will eventually be written to memory at the address
specified by the 14 active address bits provided earlier.
The CAT24C128 will acknowledge the Slave address,
address bytes and data byte. The Master then starts
the internal Write cycle by issuing a STOP condition
(Figure 5). During the internal Write cycle (tWR), the SDA
output will be tri-stated and additional Read or Write
requests will be ignored (Figure 6).
Delivery State
The CAT24C128 is shipped erased, i.e., all bytes are
FFh.
Page Write
By continuing to load data into the Page Write Buffer
after the 1st data byte and before issuing the STOP
condition, up to 64 bytes can be written simultaneously
during one internal Write cycle (Figure 7). If more data
bytes are loaded than locations available to the end of
page, then loading will continue from the beginning of
page, i.e. the page address is latched and the address
count automatically increments to and then wraps-
around at the page boundary. Previously loaded data
can thus be overwritten by new data. What is eventually
written to memory reflects the latest Page Write Buffer
contents. Only data loaded within the most recent Page
Write sequence will be written to memory.
Acknowledge Polling
The ready/busy status of the CAT24C128 can be ascer-
tained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAT24C128 will not acknowledge the Slave address.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
6
CAT24C128
Figure 5. Byte Write Sequence
BUS ACTIVITY:
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
BYTE
S
T
O
P
DATA
BYTE
SLAVE
ADDRESS
MASTER
a
–a
a –a
13
8
7
0
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
= Don't Care Bit
*
Figure 6. Write Cycle Timing
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
–a
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
SLAVE
ADDRESS
a
a –a
13
8
7 0
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
= Don't Care Bit
P ≤ 63
*
Figure 8. WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
a
a
d
7
d
0
SDA
WP
7
0
t
SU:WP
t
HD:WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
7
CAT24C128
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to
‘1’, the CAT24C128 will interpret this as a request for
data residing at the current byte address in memory.
The CAT24C128 will acknowledge the Slave address,
will immediately shift out the data residing at the current
address, and will then wait for the Master to respond.
If the Master does not acknowledge the data (NoACK)
and then follows up with a STOP condition (Figure 9),
the CAT24C128 returns to Standby mode.
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described
under Byte Write. If rather than following up the two
address bytes with data, the Master instead follows up
withanImmediateReadsequence,thentheCAT24C128
will use the 14 active addres bits to initialize the inter-
nal address counter and will shift out data residing at
the corresponding location. If the Master does not ac-
knowledge the data (NoACK) and then follows up with
a STOP condition (Figure 10), the CAT24C128 returns
to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the
1st data byte, then the CAT24C128 will continue trans-
mitting data residing at subsequent locations until the
Master responds with a NoACK, followed by a STOP
(Figure 11). In contrast to Page Write, during Sequential
Read the address count will automatically increment to
and then wrap-around at end of memory (rather than
end of page).
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
8
CAT24C128
Figure 9. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10. Selective Read Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
T
A
R
T
N
O
A
C
K
S
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
a
–a
a –a
13
8
7
0
S
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
= Don't Care Bit
*
Figure 11. Sequential Read Sequence
BUS ACTIVITY:
SLAVE
N
O
S
A T
C O
K P
MASTER
ADDRESS
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
SLAVE
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
9
CAT24C128
PACKAGE OUTLINE DRAWING
PDIP 8-Lead 300mils (L)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
3.30
IDENTIFICATION
D
TOP VIEW
E
A2
A1
A
L
c
b2
eB
e
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC MS-001.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
10
CAT24C128
SOIC 8-Lead 150mils (W)
SYMBOL
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
θ
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC MS-012.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
11
CAT24C128
TSSOP 8-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.40
E
E1
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.75
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters. Angles in degrees.
2. Complies with JEDEC MO-153.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
12
CAT24C128
UDFN 8-Pad 2 x 3mm (HU3)
D
A
DETAIL A
DAP SIZE 1.3 x 1.8
E
PIN #1
IDENTIFICATION
E2
A1
PIN #1 INDEX AREA
TOP VIEW
D2
SIDE VIEW
BOTTOM VIEW
b
SYMBOL
MIN
0.45
0.00
NOM
0.50
MAX
0.55
0.05
L
K
A
A1
A3
b
e
0.02
DETAIL A
0.127 REF
0.25
0.20
1.90
1.50
2.90
0.10
0.30
2.10
1.70
3.10
0.30
D
2.00
D2
E
1.60
A3
3.00
A
E2
e
0.20
0.50 TYP
0.10 REF
0.35
K
A1
L
0.30
0.40
FRONT VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC MO-229.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
13
CAT24C128
MSOP 8-Lead 3.0 x 3.0mm (Z)
SYMBOL
MIN
NOM
MAX
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
A
A1
A2
b
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E
E1
E1
e
3.00
0.65 BSC
0.60
L
0.40
0º
0.80
6º
L1
L2
θ
0.95 REF
0.25 BSC
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
θ
L2
L
L1
DETAIL A
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters. Angles in degrees.
2. Complies with JEDEC MO-187.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
14
CAT24C128
ORDERING INFORMATION
Prefix
Device #
24C128
Suffix
CAT
Y
I
– G
T3
Company ID
Product Number
Temperature Range
I = Industrial (-40°C to +85°C)
E = Extended (-40°C to +125°C)
T: Tape & Reel
3: 3000/Reel
24C128
Package
L: PDIP
Lead Finish
G: NiPdAu
W: SOIC, JEDEC
Y: TSSOP
Blank: Matte-Tin
HU3: UDFN (2 x 3mm)
Z: MSOP
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT24C128YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
15
CAT24C128
REVISION HISTORY
Date
Revision Comments
10/07/05
11/16/05
A
B
Initial Issue
Update Ordering Information
Add Tape and Reel Specifications
02/02/06
C
Update A.C. Characteristics
Update Ordering Information
03/13/06
04/26/06
D
E
Update A.C. Characteristics
Update Features
Update Device Description
Update Pin Configuration
Update A.C. Characteristics
Update Hardware Write Protecttion
Add Figure 6a
Add 8-Lead TSSOP Package Drawing
Update Ordering Information
Add 8-Lead TSSOP Package Marking
05/19/06
F
Update Features
Update Device Description
Update Pin Configuration
Update Ordering Information
Update D.C. Operating Characteristics
Update Pin Impedance Characteristics
Update A.C. Characteristics
Add Power-On Reset (POR)
Update 8-Lead PDIP Package Drawing
Update 8-Lead SOIC Package Drawing
Update 8-Lead TSSOP Package Drawing
Update Tape and Reel
08/11/06
G
Update Features
Update D.C. Operating Characteristics
Update Pin Impedance Characteristics
Update A.C. Test Conditions
Update Power-On Reset (POR)
Update Pin Description
Update I2C Bus Protocol
Update Device Addressing
Update Acknowledge
Update Write Operations
Update Byte Write
Update Page Write
Update Acknowledge Polling
Add Delivery State
Update Read Operations
Update Selective Read
Update Sequential Read
Update Figure 1, 2, 3, 5, 6, 6a, 7, 8, 9 and 10
Update Part Marking
Update Ordering Information
08/21/07
H
Add Extended temperature range
Update D.C. Operating Characteristics table
Update Package Outline Drawings and add UDFN Package Outline Drawing
Add MD- to document number
08/29/07
09/18/07
I
Update UDFN Package Outline Drawing to include “e” dimension.
Add MSOP Package Outline Drawing
J
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-1103, Rev. J
16
CAT24C128
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled “Advance Information” or “Preliminary” and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
© Catalyst Semiconductor, Inc.
Doc No. MD-1103, Rev. J
17
Characteristics subject to change without notice
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: MD-1103
Revison:
J
Issue date:
09/18/07
www.catsemi.com
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