CAT24C16YI-GT3 [CATALYST]
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM; 1 - KB ， 2 - KB， 4 KB ， 8 KB和16 KB的CMOS串行EEPROM
| 型号： | CAT24C16YI-GT3 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM |
| 文件： | 总17页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C01/02/04/08/16
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
FEATURES
DEVICE DESCRIPTION
■ Supports Standard and Fast I2C Protocol
■ 1.8 V to 5.5 V Supply Voltage Range
■ 16-Byte Page Write Buffer
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each.All devices support
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
■ Hardware Write Protection for entire memory
■ Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Industrial temperature range
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
■ RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
For Ordering Information details, see page 16.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (W)
TSSOP (Y)
MSOP (Z)
V
CC
TDFN (VP2)
TSOT-23 (TD)
CAT24C16 / 08 / 04 / 02 01
/
SCL
1
2
3
5
WP
NC / NC / NC / A
A
A
A
1
2
3
4
8
7
6
5
V
CC
0 /
1 /
2 /
0
1
2
SCL
NC / NC / A / A
1
WP
V
SS
NC / A / A / A
SCL
SDA
2
2
A , A , A
CAT24Cxx
SDA
2
1
0
SDA
4
V
V
CC
SS
WP
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
V
SS
A0, A1, A2
SDA
SCL
WP
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
VCC
VSS
Ground
NC
No Connect
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
1
CAT24C01/02/04/08/16
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
(4)
NEND
TDR
Endurance
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz
1
mA
ICCW
ISB
Write Current
Write, fSCL = 400 kHz
1
mA
All I/O Pins at GND or VCC
μA
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
1
1
IL
Pin at GND or VCC
μA
V
VIL
VIH
-0.5
VCC x 0.3
VCC x 0.7 VCC + 0.5
V
VOL1
VOL2
0.4
0.2
V
VCC ≥ 2.5 V, IOL = 3.0 mA
VCC < 2.5 V, IOL = 1.0 mA
V
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Conditions
Max
8
Units
pF
(3)
CIN
SDA I/O Pin Capacitance
VIN = 0 V
(3)
CIN
IWP
Input Capacitance (other pins)
WP Input Current
VIN = 0 V
6
pF
(5)
VIN < VIH, VCC = 5.5 V
VIN < VIH, VCC = 3.3 V
VIN < VIH, VCC = 1.8 V
VIN > VIH
200
150
100
1
μA
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
© 2006 by Catalyst Semiconductor, Inc.
Doc. No. 1115, Rev. C
2
Characteristics subject to change without notice
CAT24C01/02/04/08/16
A.C. CHARACTERISTICS(1)
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C.
Standard
Fast
Symbol
Parameter
Min
Max
Min
Max
Units
FSCL
Clock Frequency
100
400
kHz
tHD:STA
tLOW
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
ns
ns
μs
μs
ms
ms
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
4.7
0
Data In Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
1000
300
300
300
(2)
tF
tSU:STO
tBUF
4
0.6
1.3
4.7
tAA
3.5
0.9
tDH
100
100
Ti(2)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
tSU:WP
tHD:WP
tWR
0
0
WP Hold Time
2.5
2.5
Write Cycle Time
5
1
5
1
(2, 3)
tPU
Power-up to Ready Mode
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
≤ 50 ns
Input Rise and Fall Times
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1115, Rev. C
3
CAT24C01/02/04/08/16
I2C BUS PROTOCOL
POWER-ON RESET (POR)
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDAline to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Each CAT24Cxx* incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
A CAT24Cxx device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDAwhile SCLis HIGH. The STARTacts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
* For common features, the CAT24C01/02/04/08/16 will be refered
to as CAT24Cxx
PIN DESCRIPTION
SCL:The Serial Clock input pin accepts the Serial Clock
generated by the Master.
Device Addressing
SDA: The Serial Data I/O pin receives input data and
transmitsdatastoredinEEPROM.Intransmitmode,this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bitserialSlaveaddress.FornormalRead/Writeopera-
tions, the first 4 bits of the Slave address are fixed at
1010 (Ah). The next 3 bits are used as programmable
address bits when cascading multiple devices and/or as
internal address bits. The last bit of the slave address,
R/W, specifies whether a Read (1) or Write (0) operation
is to be performed. The 3 address space extension bits
are assigned as illustrated in Figure 2. A2, A1 and A0
must match the state of the external address pins, and
a10, a9 and a8 are internal address bits.
A0, A1 and A2: The Address inputs set the device ad-
dresswhencascadingmultipledevices.Whennotdriven,
these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle.As long as the Master acknowledges
thedata, theSlavewillcontinuetransmitting.TheMaster
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
FUNCTIONAL DESCRIPTION
TheCAT24CxxsupportstheInter-IntegratedCircuit(I2C)
Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by
a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24Cxx acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
4
CAT24C01/02/04/08/16
Figure 1. START/STOP Conditions
SCL
SDA
START
STOP
CONDITION
CONDITION
Figure 2. Slave Address Bits
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A
A
A
A
A
A
R/W
R/W
R/W
R/W
CAT24C01 and CAT24C02
CAT24C04
2
2
2
1
1
9
9
0
8
8
8
a
a
a
a
a
CAT24C08
a
CAT24C16
10
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
t
BUF
t
t
AA
DH
SDA OUT
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1115, Rev. C
5
CAT24C01/02/04/08/16
WRITE OPERATIONS
Byte Write
Hardware Write Protection
In Byte Write mode, the Master sends the START condi-
tion and the Slave address with the R/W bit set to zero
to the Slave.After the Slave generates an acknowledge,
the Master sends the byte address that is to be written
into the address pointer of the CAT24Cxx. After receiv-
ing another acknowledge from the Slave, the Master
transmits the data byte to be written into the addressed
memory location. The CAT24Cxx device will acknowl-
edge the data byte and the Master generates the STOP
condition, at which time the device begins its internal
Write cycle to nonvolatile memory (Figure 5). While this
internal cycle is in progress (tWR), the SDA output will
be tri-stated and the CAT24Cxx will not respond to any
request from the Master device (Figure 6).
WiththeWPpinheldHIGH,theentirememoryisprotected
against Write operations. If the WP pin is left floating or
is grounded, it has no impact on the operation of the
CAT24Cxx. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first
data byte (Figure 8). If the WP pin is HIGH during the
strobe interval, the CAT24Cxx will not acknowledge the
data byte and the Write request will be rejected.
Delivery State
The CAT24Cxx is shipped erased, i.e., all bytes are
FFh.
Page Write
The CAT24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 7).
ThePageWriteoperationisinitiatedinthesamemanner
as the Byte Write operation, however instead of termi-
nating after the data byte is transmitted, the Master is
allowed to send up to fifteen additional bytes.After each
byte has been transmitted the CAT24Cxx will respond
with an acknowledge and internally increments the four
low order address bits. The high order bits that define
the page address remain unchanged. If the Master
transmits more than sixteen bytes prior to sending the
STOP condition, the address counter ‘wraps around’ to
the beginning of page and previously transmitted data
will be overwritten. Once all sixteen bytes are received
and the STOP condition has been sent by the Master,
the internal Write cycle begins. At this point all received
data is written to the CAT24Cxx in a single write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the host’s
writeoperation, theCAT24Cxxinitiatestheinternalwrite
cycle. TheACKpollingcanbeinitiatedimmediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still
busy with the write operation, NoACK will be returned. If
theCAT24Cxxhascompletedtheinternalwriteoperation,
an ACK will be returned and the host can then proceed
with the next read or write operation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
6
CAT24C01/02/04/08/16
Figure 5. Byte Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
ADDRESS
BYTE
DATA
BYTE
T
O
P
SLAVE
ADDRESS
a
÷ a
d ÷ d
7 0
7
0
S
P
A
C
K
A
C
K
A
C
K
SLAVE
* For the CAT24C01 a = 0
7
Figure 6. Write Cycle Timing
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
ADDRESS
BYTE
SLAVE
ADDRESS
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
n = 1
P ≤ 15
Figure 8. WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
SDA
a
a
d
d
0
7
0
7
t
SU:WP
WP
t
HD:WP
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1115, Rev. C
7
CAT24C01/02/04/08/16
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set
to ‘1’, the CAT24Cxx will interpret this as a request for
data residing at the current byte address in memory.
The CAT24Cxx will acknowledge the Slave address,
will immediately shift out the data residing at the current
address, and will then wait for the Master to respond.
If the Master does not acknowledge the data (NoACK)
and then follows up with a STOP condition (Figure 9),
the CAT24Cxx returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read opera-
tion. The Master device first performs a ‘dummy’ write
operation by sending the START condition, slave ad-
dress and byte address of the location it wishes to read.
After the CAT24Cxx acknowledges the byte address,
the Master device resends the START condition and
the slave address, this time with the R/W bit set to one.
The CAT24Cxx then responds with its acknowledge and
sends the requested data byte. The Master device does
not acknowledge the data (NoACK) but will generate a
STOP condition (Figure 10).
Sequential Read
IfduringaReadsession,theMasteracknowledgesthe1st
data byte, then the CAT24Cxx will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure
11). In contrast to Page Write, during Sequential Read
the address count will automatically increment to and
then wrap-around at end of memory (rather than end
of page). In the CAT24C01, the internal address count
will not wrap around at the end of the 128 byte memory
space.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
8
CAT24C01/02/04/08/16
Figure 9. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10. Selective Read Sequence
N
O
S
T
A
R
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11. Sequential Read Sequence
N
O
BUS ACTIVITY:
SLAVE
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
MASTER
ADDRESS
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1115, Rev. C
9
CAT24C01/02/04/08/16
PACKAGE OUTLINE
8-lead 300 MIL Wide Plastic DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
4.57
0.38
3.05
0.36
1.14
9.02
7.62
6.09
3.81
0.56
1.77
10.16
8.25
7.11
0.46
b2
D
E
7.87
6.35
E1
e
2.54 BSC
eB
L
7.87
0.115
9.65
0.150
0.130
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC Standard MS001.
(3) Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
10
CAT24C01/02/04/08/16
8-lead 150 Mil Wide Soic (W)
E1
E
h x 45
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
θ1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MS-012 dimensions.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1115, Rev. C
11
CAT24C01/02/04/08/16
8-Lead TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
θ
1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MO-153.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
12
CAT24C01/02/04/08/16
8-Lead MSOP (Z)
E1
E
e
D
GAUGE
PLANE
A2
A
L2
L
b
A1
L1
SYMBOL
MIN
NOM
MAX
1.1
A
A1
A2
b
0.05
0.75
0.28
0.10
0.85
0.33
0.15
0.95
0.38
c
D
2.90
4.80
2.90
3.00
4.90
3.00
3.10
5.00
3.10
E
E1
e
0.65 BSC
0.45
L
0.35
0.55
For current Tape and Reel information,
download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
L1
L2
0°
6°
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MS-187.
(3) Stand off height/coplanarity are considered as special characteristics.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1115, Rev. C
13
CAT24C01/02/04/08/16
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
A1
D
D2
A2
A3
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.02
E2
0.55
0.20 REF
0.25
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
PIN 1 ID
D
2.00
D2
E
1.40
3.00
E2
e
1.30
L
0.50 TYP
0.30
L
0.20
0.40
b
e
3 x e
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MO-229.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
14
CAT24C01/02/04/08/16
5-Lead TSOT-23 (TD)
e
e
E
E1
E1
e1
D
GAUGE
PLANE
A2
c
A
L2
θ
L
A1
b
L1
SYMBOL
MIN
—
NOM
—
MAX
1.0
A
A1
A2
b
0.01
0.80
0.30
0.12
0.05
0.1
0.87
0.9
—
0.45
0.20
c
0.15
D
2.90 BSC
2.80 BSC
1.60 BSC
0.95 BSC
1.90 BSC
0.40
E
E1
e
e1
L
0.30
0.50
L1
L2
θ
0.60 REF
0.25 BSC
0°
8°
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MO-193.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1115, Rev. C
15
CAT24C01/02/04/08/16
EXAMPLE OF ORDERING INFORMATION
Prefix
Device #
24C16
Suffix
CAT
Y
I
–
G
T3
Company ID
Product Number
24C01
Temperature Range
I = Industrial (-40°C to +85°C)
T: Tape & Reel
3: 3000/Reel
24C02
24C04
24C08
24C16
Lead Finish
G: NiPdAu
Blank: Matte-Tin
Package
L: PDIP
W: SOIC, JEDEC
Y: TSSOP
Z: MSOP (4)
VP2: TDFN
TD: TSOT
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames.
(3) The device used in the above example is a CAT24C16YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For availability, please contact your nearest Catalyst Semiconductor Sales Office.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
16
REVISION HISTORY
Date
Revision Comments
07/18/06
07/31/06
11/29/06
A
B
C
Combine 5 data sheets into one data sheet.
Update Package Marking
Update Features
Update Pin Configuration
Update Functional Symbol
Added 8-Lead MSOP Package Outline
Remove Package Marking
Update Example of Ordering Information
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CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
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Corporate Headquarters
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Publication #: 1115
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Revison:
C
Issue date:
11/29/06
相关型号：
CAT24C16YIGT3
16KX1 I2C/2-WIRE SERIAL EEPROM, PDSO8, 4.40 X 3 MM, HALOGEN FREE AND ROHS COMPLIANT, MO-153, TSSOP-8
ONSEMI
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