CAT24C208WI-TE13 [CATALYST]
EEPROM, 1KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, MS-012, SOIC-8;
| 型号： | CAT24C208WI-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 1KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, MS-012, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
E
CAT24C208
8K (1K x 8) -Bit Dual Port Serial EEPROM for VESA Plug and Play Applications
in LCD Projectors and Monitors
TM
FEATURES
■ 400 kHz I2C bus compatible*
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Complies with VESA E-EDID, E-DDC, DI-EXT
and M1 specifications
■ 8-pin DIP, SOIC, TSSOP or MSOP packages
- Green package option
■ 3V to 5.5V volt operation
■ Industrial and extended temperature ranges
■ Low power CMOS technology
■ 16-byte page write buffer
■ Self-timed write cycle with auto-clear
DESCRIPTION
Using Catalyst's advanced CMOS technology which
substantially reduces device power requirements, the
CAT24C208 can be powered from either of two
independent VCC inputs.
The CAT24C208 is an 8k-bit Dual Port Serial CMOS
EEPROM internally organized as 1k words of 8 bits
each. The CAT24C208 features a 16-byte page write
buffer and can be accessed from either of two separate
I2C compatible ports, DSP (SDA, SCL) and DDC (SDA,
SCL) which conform to the VESA E-EDID EEPROM
Standard.
The CAT24C208 operates over the full industrial and
extended temperature range and is available in
miniature 8-pin DIP, SOIC, TSSOP and MSOP
packages.
Arbitration between the two interface ports is automatic
and allows the appearance of individual access to the
memory from each interface.
BLOCK DIAGRAM
DSP V
CC
DDC V
CC
ARBITRATION
LOGIC
D
E
C
O
D
E
R
S
D
E
C
O
D
E
R
S
1K X 8
MEMORY
ARRAY
DDC
CONTROL
LOGIC
DISPLAY
CONTROL
LOGIC
DSP SCL
DSP SDA
DDC SCL
DDC SDA
CONFIGURATION
REGISTER
EDID SEL
V
SS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1044, Rev. D
1
CAT24C208
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DSP V
DDC V
CC
DSP V
DDC V
CC
CC
CC
DSP SCL
DSP SDA
EDID SEL
DDC SCL
DDC SDA
DSP SCL
EDID SEL
DDC SCL
DDC SDA
DSP SDA
V
V
SS
SS
MSOP Package (R, Z)
TSSOP Package (U, Y)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DSP V
DDC V
CC
DSP V
DDC V
CC
CC
CC
DSP SCL
EDID SEL
DDC SCL
DDC SDA
DSP SCL
DSP SDA
EDID SEL
DDC SCL
DDC SDA
DSP SDA
V
V
SS
SS
PIN DESCRIPTION
Pin Number
Pin Name
DSP VCC
DSP SCL
Function
1
2
Device power from display controller
The CAT24C208 DSP serial clock bidirectional pin is used to clock all
data transfers into or out of the device DSP SDA pin and is also used to
block DSP Port access when DDC Port is active.
3
DSP SDA
DSP Serial Data/Address. The bidirectional DSP serial data/address pin
is used to transfer data into and out of the device from a display
controller. The DSP SDA pin is an open drain output and can be wire-
OR'ed with other open drain or open collector outputs.
4
5
VSS
Device ground.
DDC SDA
DDC Serial Data/Address. The bidirectional DDC serial data/address
pin is used to transfer data into and out of the device from a DDC host.
The DDC SDA pin is an open drain output and can be wire-OR'ed with
other open drain or open collector outputs.
6
7
8
DDC SCL
EDID SEL
DDC VCC
The CAT24C208 DDC serial clock bidirectional pin is used to clock all
data transfers into or out of the device DDC SDA pin, and is used to
block DDC Port for access when DSP Port is active.
EDID select. The CAT24C208 EDID select input selects the active bank
of memory to be accessed via the DDC SDA/SCL interface as set in
the configuration register.
Device power when powered from a DDC host.
Doc. No. 1044, Rev. D
2
CAT24C208
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ............ -2.0V to +VCC + 2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
Reliability Characteristics
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
4000
100
(3)
VZAP
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
V
= 3V to 5.5V, unless otherwise specified.
CC
Symbol Parameter
ICC Power Supply Current
ISB
Test Conditions
Min
Typ
Max
3
Units
mA
fSCL = 100 KHz
Standby Current (VCC = 5.0V)
Input Leakage Current
VIN = GND or either
DSP or DDC VCC
50
µA
ILI
VIN = GND to either
DSP or DDC VCC
10
10
µA
µA
ILO
Output Leakage Current
VOUT = GND to either
DSP or DDC VCC
VIL
VIH
Input Low Voltage
Input High Voltage
– 1
VCC x 0.7
0.05
VCC x 0.3
VCC + 0.5
V
V
VHYS Input Hysteresis
V
VOL1
VCCL1
VCCL2
Output Low Voltage (VCC = 3V)
IOL = 3 mA
0.4
V
Leakage DSP VCC to DDC VCC
Leakage DDC VCC to DSP VCC
+100
+100
µA
µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1044, Rev. D
3
CAT24C208
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol Parameter
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max Units
(1)
CI/O
Input/Output Capacitance (Either DSP or DDC SDA)
Input Capacitance (EDID, Either DSP or DDC SCL)
8
6
pF
pF
(1)
CIN
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
V
= 3V to 5.5V, unless otherwise specified.
CC
Read & Write Cycle Limits
Symbol
FSCL
Parameter
Min
Max
Units
Clock Frequency
400
100
1
kHz
ns
TI(1)
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
tAA
µs
(1)
tBUF
Time the Bus Must be Free Before a New Transmission
Can Start
1.2
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
0.6
1.2
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time (for a Repeated Start
Condition)
tHD:DAT
tSU:DAT
Data In Hold Time
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.3
(1)
tF
300
tSU:STO
tDH
0.6
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Power-Up Timing(1)(2)
Symbol
tPUR
Parameter
Min
Typ
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. Duringthewritecycle, thebusinterfacecircuitsaredisabled, SDAisallowedtoremainhigh, andthedevicedoes
not respond to its slave address.
Doc. No. 1044, Rev. D
4
CAT24C208
interface, the memory space appears as two 500 byte
banks of memory, with 2 segments each 00h and 01h in
the upper and lower bank, see Table 1.
FUNCTIONAL DESCRIPTION
The CAT24C208 has a total memory space of 1K bytes
which is accessible from either of two I2C interface
ports, (DSP_SDA and DSP_SCL) or (DDC_SDA and
DDC_SCL), and with the use of segment pointer at
address 60h. On power up and after any instruction, the
segment pointer will be in segment 00h for DSP and in
segment 00h of the bank selected by the configuration
register for DDC.
Each bank of memory can be used to store an E-EDID
data structure. However, only one bank can be read
through the DDC port at a time. The active bank of
memory (that is, the bank that appears at address A0h
on the DDC port) is controlled through the configuration
register at 62/63h and the EDID_SEL pin.
NowriteoperationsarepossiblefromtheDDCinterface
unless the DDC Write Enable bit is set (WE = 1) in the
device configuration register at device address 62h.
The entire memory appears as contiguous memory
space from the perspective of the display interface
(DSP_SDA and DSP_SCL), see Table 2, and Figures
11 to Figure 18 for a complete description of the DSP
Interface.
The device automatically arbitrates between the two
interfaces to allow the appearance of individual access
to the memory from each interface.
A configuration register at addresses 62/63h is used to
configure the operation and memory map of the device
as seen from the DDC interface, (DDC_SDA and
DDC_SCL).
In a typical E-EDID application the EDID_SEL pin is
usually connected to the “Analog Cable Detect” pin of a
VESA M1 compliant, dual-mode (analog and digital)
display. In this manner, the E-EDID appearing at ad-
dress A0h on the DDC port will be either the analog or
digital E-EDID, depending on the state of the “Analog
Cable Detect” pin (pin C3 of the M1-DA connector). See
Figure 1.
Read and write operations can be performed on any
location within the memory space from the display DSP
interface regardless of the state of the EDID SEL pin or
the activity on the DDC interface. From the DDC
Figure 1.
28
DDC +5V
47.5K
+5V DC
(SUPPLIED
BY DISPLAY)
10K
8
7
6
5
1
2
3
4
C3
27
26
I2C TO PROJECTOR/MONITOR
DISPLAY CONTROLLER
E-EDID
EEPROM
TO HOST
CONTROLLER
DDC CLK
DDC DATA
FUSE, RESISTOR
OR OTHER CURRENT
LIMITING DEVICE
REQUIRED IN ALL M1 DISPLAYS
RELAY CONTACTS SHOWN IN
DE-ENERGIZED POSITION
8
HPD
2A MAX
Table 1: DDC Interface
Table 2: DSP Interface
MEMORY ARRAY
MEMORY ARRAY
Segment 1
256 Bytes
Segment 3
256 Bytes
11
10
01
Upper
00
00
00
Bank
Segment 0
256 Bytes
Segment 2
256 Bytes
01
00
01
Segment 1
256 Bytes
Segment 1
256 Bytes
Lower
Bank
00
00
Segment 0
256 Bytes
Segment 0
256 Bytes
Segment Pointer
Segment Pointer
No Segment Pointer
Address by
No Segment Pointer
Configuration Register
(see Figure 19)
Doc. No. 1044, Rev. D
5
CAT24C208
I2C Bus Protocol
Acknowledge
ThefollowingdefinesthefeaturesoftheI2Cbusprotocol:
After a successful data transfer, each receiving device is
requiredtogenerateanacknowledge.Theacknowledging
devicepullsdowntherespectiveSDAlineduringtheninth
clock cycle, signaling that it received the 8 bits of data.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
The CAT24C208 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
either SDA when the respective SCL is HIGH. The
CAT24C208 monitors the SDA and SCL lines and will
not respond until this condition is met.
When the CAT24C208 is in a READ mode it transmits 8
bits of data, releases the respective SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24C208 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
After an unsuccessful data transfer an acknowledge will
not be issued (NACK) by the slave (CAT24C208), and
the master should abort the sequence. If continued the
device will read from or write to the wrong address in the
two instruction format with the segment pointers.
Figure 2. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Doc. No. 1044, Rev. D
6
CAT24C208
DEVICE ADDRESSING
DDC Interface
Both the DDC and DSP interfaces to the device are based on the I2C bus serial interface. All memory space operations
are done at the A0/A1 DDC address pair. As such, all write operations to the memory space are done at DDC address
A0h and all read operations of the memory space are done at DDC address A1h.
Figure 3 shows the bit sequence of a random read from anywhere within the memory space. The word offset
determines which of the 256 bytes within segment 00h is being read. Here the segment 00h can be at the lower or
upper bank depending on the configuration register.
Sequential reads can be done in much the same manner by reading successive bytes after each acknowledge without
generating a stop condition. See Figure 4. The device automatically increments the word offset value (8-bit value) and
with wraparound in the same segment 00h to read maximum of 256 bytes.
Figure 3. Random Access Read (Segment 00h only)
WORD OFFSET
START
1010 0000
ACK
A7 - A0 ADDRESS
ACK
START
1010 0001
ACK
DATA
NOACK
STOP
Figure 4. Sequential Read (Segment 00h only)
WORD OFFSET
A7 - A0
ADDRESS
START
1010 0000 ACK
ACK START 1010 0001 ACK
DATA0
ACK
......... DATAN NOACK STOP
Figures 5 and 6 show the byte and page write respectively. The configuration register must have the WE bit set to 1
prior to any write on DDC Port. Only the segment 00h can be accessed of either lower or upper bank.
Figure 5. Byte Write (Segment 00h only)
WORD OFFSET
START
1010 0000
ACK
A7 - A0 ADDRESS
ACK
DATA
ACK
STOP
Figure 6. Page Write (Segment 00h only)
WORD OFFSET
START
1010 0000
ACK
A7 - A0 ADDRESS
ACK
DATA0
ACK
.........
DATA15
ACK
STOP
Doc. No. 1044, Rev. D
7
CAT24C208
Thesegmentpointerisattheaddress60handiswrite-only. Thismeansthatamemoryaccessat61hwillgiveundefined
results. The segment pointer is a volatile register. The device configuration register at 62/63 (hex) is a non-volatile
register. The configuration register will be shipped in the erased (set to FFh) state.
The segment pointer is used to expand the available DDC address space while maintaining backward compatibility with
older DDC interfaces such as DDC2B. For each value of the 8-bit segment pointer one segment (256 bytes) is available
at the A0/A1 pair. The standard DDC 8-bit address is sufficient to address each of the 256 bytes within a segment. Note
that if the segment pointer is set to 00h then the device will behave like a standard DDC2B EEPROM.
Read and write with segment pointer can expand the addressable memory to 512 bytes in each bank with wraparound
to the next segment in the same bank only. The two banks can be individually selected by the configuration register and
EDID Sel pin, as shown in figure 19. The segments are selected by the two bits S1S0 = 00 or 01 in the segment address.
Figures 7 to 10 show the random read, sequential read, byte write and page write.
Figure 7. Random Access Read
START
START
0110 0000
1010 0000
ACK
ACK
xxxx xxS1S0 Segment ADDRESS
A7 - A0 ADDRESS
ACK
ACK
START
1010 0001
ACK
DATA NOACK STOP
Figure 8. Sequential Read
START 0110 0000 ACK xxxx xxS1S0 Segment ADDRESS
ACK
START 1010 0000 ACK
A7 - A0 ADDRESS
ACK START 1010 0001 ACK DATA0 ACK ...... DATAN NOACK STOP
Figure 9. Byte Write
START 0110 0000 ACK xxxx xxS1S0 Segment ADDRESS
ACK
START 1010 0000 ACK
A7 - A0 ADDRESS
ACK
DATA
ACK
STOP
Figure 10. Page Write
START 0110 0000
START 1010 0000
ACK
ACK
xxxx xxS1S0 Segment ADDRESS
ACK
A7 - A0 ADDRESS ACK DATA0 ACK
..........
DATA15
ACK
STOP
Doc. No. 1044, Rev. D
8
CAT24C208
DSP Interface
The DSP interface is similar to I2C bus serial interface. Without the segment pointer, the maximum accessible memory
space is 256 bytes of segment 00h only. In the sequential mode the wrap around will be in the same segment also.
Figures 11 to 14 show the read and write on the DSP Port.
Figure 11. Random Access Read
START
1010 0000
ACK
A7 - A0 ADDRESS
ACK
START
1010 0001
ACK
DATA
NOACK STOP
Figure 12. Sequential Read
START 1010 0000 ACK A7 - A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ..... DATAN NOACK STOP
Figure 13. Byte Write
START
1010 0000
ACK
A7 - A0 ADDRESS
ACK
DATA
ACK
STOP
Figure 14. Page Write
START 1010 0000 ACK A7 - A0 ADDRESS ACK DATA0
ACK
......
DATA15
ACK STOP
The segment pointer is used to expand the available DSP port addressable memory to 1k bytes, divided into four
segments of 256 bytes each. The four segments are selected by two bits S1S0 = 00, 01, 10, 11 in the segment address.
Figures 15 to 18 show the random read, sequential read, byte write and page write.
Figure 15. Random Access Read
START 0110 0000 ACK
START 1010 0000 ACK
xxxx xxS1S0 Segment ADDRESS
A7 - A0 ADDRESS ACK
ACK
START 1010 0001 ACK
DATA
NOACK STOP
Figure 16. Sequential Read
START 0110 0000 ACK
xxxx xxS1S0 Segment ADDRESS
ACK
START 1010 0000 ACK
A7 - A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ....... DATAN NOACK STOP
Figure 17. Byte Write
START 0110 0000 ACK
START 1010 0000 ACK
xxxx xxS1S0 Segment ADDRESS
A7 - A0 ADDRESS ACK
ACK
DATA
ACK STOP
Figure 18. Page Write
START 0110 0000 ACK
START 1010 0000 ACK
xxxx xxS1S0 Segment ADDRESS
A7 - A0 ADDRESS ACK DATA0
ACK
ACK
......
DATA15
ACK
STOP
Doc. No. 1044, Rev. D
9
CAT24C208
it low, holding off activity on the other port (by stretching
the clock on that port). When the initiating SCL line has
remained high for one full second, the arbitration logic
assumes that the initiating devices is finished and
releases the other SCL line. If the non-initiating device
has been waiting for access, it can now read or write the
device.
ARBITRATION
The device performs a simplistic arbitration between the
DDCanddisplayinterfaces.Whilethearbitrationscheme
described is not foolproof, it does prevent most errors.
The arbitration logic uses “clock stretching”, an I2C bus
term, to hold off writes from one port while the other port
is active.
For this scheme to work properly, both the DDC and
DSP devices must properly implement clock stretching
as defined by the I2C specification. Additionally, it is very
important that when writing to the device that the SCL
line never remains high longer than 1 second, until the
write is complete. This prevents the other port from
having access until the device is fully written.
Arbitration logic within the device monitors activity on
DDC_SCLandDSP_SCL.WhenbothI2Cportsareidle,
DDC_SCL and DSP_SCL are both high and the
arbitration logic is inactive. When either DDC_SCL or
DSP_SCL is pulled low, initiating a read or write, the
arbitration logic pulls down the other SCL line and holds
CONFIGURATION REGISTER
MSB
LSB
7
6
5
4
3
2
1
0
Register Function
X
X
X
X
WE
AB1
AB0
NB
Configuration Register
Function Description:
NB:
AB0:
Number of memory banks in DDC port memory map. 0 = 2 Banks, 1 = 1 Bank
Active Bank Control Bit 0 (See Figure 19)
AB1:
Active Bank Control Bit 1 (See Figure 19)
WE DDC:
Write Enable 0 = Write Disabled, 1= Write Enabled
Note: WE affects only write operations from the DDC port, not the display port. The display port always has write access.
Figure 19. Configuration Register Truth Table
EDID
AB1
AB0
NB
Active Bank
Select Pin
0
0
1
1
X
X
X
0
0
0
0
0
1
0
1
Lower Bank
Upper Bank
X
X
X
Lower Bank
1
Upper Bank
X
Lower (only) Bank
The configuration register is a non-volatile register and is available from either DSP or DDC port at address 62h/63h
for write and read resp.
Figure 20. Read Configuration Register
START
0110 0011
ACK
DATA
NO ACK
STOP
Figure 21. Write Configuration Register
START
0110 0010
ACK
DUMMY ADDRESS
ACK
XXXX WE AB1 AB0 NB
ACK
STOP
Doc. No. 1044, Rev. D
10
CAT24C208
ORDERING INFORMATION
Prefix
Device #
24C208
Suffix
CAT
J
I
TE13
Temperature Range
I = Industrial (-40 to 85 C)
E = Extended (-40 to 125 C)
Product Number
24C208: 8K
Tape & Reel
Optional
Company ID
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a CAT24C208JI-TE13 (SOIC, Industrial Temperature, 3 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
Doc. No. 1044, Rev. D
11
CAT24C208
PACKAGING INFORMATION
8 Lead PDIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
D
0.120 (3.05)
0.150 (3.81)
0.180 (4.57) MAX
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
—
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Dimension D
Min
0.355 (9.02)
Pkg
Max
8L
0.400 (10.16)
Doc. No. 1044, Rev. D
12
CAT24C208
PACKAGING INFORMATION
8 Lead 150 mil Wide SOIC (J, W)
0.149 (3.80)
0.1574 (4.00)
0.2284 (5.80)
0.2440 (6.20)
0.1890 (4.80)
0.1968 (5.00)
0.0532 (1.35)
0.0688 (1.75)
0.050 (1.27) BSC
0.0040 (0.10)
0.0098 (0.25)
0.013 (0.33)
0.020 (0.51)
0.0099 (0.25)
0.0196 (0.50)
X 45
˚
0.0075 (0.19)
0.0098 (0.25)
0˚-8˚
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc. No. 1044, Rev. D
13
CAT24C208
PACKAGING INFORMATION
8 Lead TSSOP (U, Y)
Notes:
1. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc. No. 1044, Rev. D
14
CAT24C208
PACKAGING INFORMATION
8 Lead MSOP (R, Z)
0.38
0.28
0.0150
0.0110
0.1970
0.1890
5.00
4.80
S
0.0256 [0.65] BSC
3.10
2.90
0.1220
0.1142
0.0374
0.0295
0.95
0.75
0.0433 [1.10] MAX.
0.0059
0.0020
0.15
0.05
0.039 [0.10] MAX.
S
S
0.0150
0.0110
0.38
0.28
WITH PLATING
0.0091 0.23
0.0051 0.13
0.0050 [0.127]
0.1220
0.1142
3.10
2.90
0.0276
0.0157
0.70
0.40
0˚ - 6˚
WITH PLATING
BASE METAL
0.0118 [0.30] REF.
SECTION A - A
Doc. No. 1044, Rev. D
15
REVISION HISTORY
Date
Rev.
Reason
2/18/2004
C
Changed volt operation to 3V to 5.5V
Updated Block Diagram
Updated Pin Descriptions
Updated DC Operating Characteristics
Updated AC Characteristics
Changed/Added figures 3 - 21
Updated Ordering Information
Updated Function Description
Updated Oedering Information
03/25/2005
D
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Revison:
Issue date:
Type:
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03/25/05
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相关型号：
CAT24C208YE-TE13
IC 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, GREEN, MO-153AA, TSSOP-8, Programmable ROM
CATALYST
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