CAT24C21W-TE13 [CATALYST]
128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, LEAD AND HALOGEN FREE, SOIC-8;
| 型号： | CAT24C21W-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, LEAD AND HALOGEN FREE, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总11页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT24C21
1-kb Dual Mode Serial EEPROM for VESA™ "Plug-and-Play"
TM
FEATURES
■ DDC1TM/DDC2TM interface compliant for
■ Low power CMOS technology
monitor identification
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ 400 kHz I2C bus compatible*
■ 2.5 to 5.5 volt operation
■ 16-byte page write buffer
■ Hardware write protect
■ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN
packages
■ Industrial temperature range
DESCRIPTION
by the SCL clock input, with both modes sharing a
commonSDAinput/output(I/O).Thetransmit-onlymode
is a read-only mode, while the bi-directional mode is a
read and write mode following the I2C protocol. In write
mode the CAT24C21 features a 16-byte page write
buffer.Thedeviceisavailablein8-inDIP,SOIC,TSSOP,
MSOP and TDFN packages.
The CAT24C21 is a 1-kb Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. The
device complies with the Video Electronics Standard
Association's(VESA™),DisplayDataChannel(DDC™)
standards for "Plug-and-Play" monitors. The "transmit-
only" mode (DDC1™) is controlled by the VCLK clock
inputandthe"bi-directional"mode(DDC2™)iscontrolled
PIN CONFIGURATION
FUNCTIONAL SYMBOL
DIP Package (P, L)
SOIC Package (J, W)
V
CC
1
2
3
4
8
7
6
5
NC
NC
NC
V
1
2
3
4
8
7
6
5
NC
NC
NC
V
CC
CC
VCLK
VCLK
SCL
SCL
SCL
V
SDA
V
SDA
SS
SS
CAT24C21
SDA
MSOP Package (R, Z)
TDFN Package (RD4, ZD4)
VCLK
1
2
3
4
8
7
6
5
NC
NC
NC
V
CC
VCLK
1
2
3
4
NC
NC
NC
8
7
6
5
V
CC
VCLK
SCL
SCL
V
SS
V
SDA
V
SDA
SS
SS
3 mm x 3 mm
Top View
PIN FUNCTIONS
TSSOP Package (U, Y)
Pin Name
Function
1
2
3
4
8
7
6
5
NC
NC
NC
V
NC
No Connect
CC
VCLK
SCL
SDA
SCL
VCLK
VCC
VSS
Serial Data/Address
V
SS
SDA
Serial Clock (bi-directional mode)
Serial Clock (transmit-only mode)
Power Supply
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus
Protocol.
Ground
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1032, Rev. L
1
CAT24C21
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V
VCC with Respect to Ground .............. -2.0 V to +7.0 V
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current(2) ....................... 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Units
(3)(*)
NEND
Endurance
Program/Erase Cycles
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
Years
Volts
mA
(3)
VZAP
2000
(3)(4)
ILTH
100
(*) Page Mode, V = 5 V, 25˚C
CC
D.C. OPERATING CHARACTERISTICS
V
= 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.
CC
Symbol
ICC
Parameter
Test Conditions
fSCL = 400 kHz
Min
Max
Units
mA
µA
µA
µA
V
Power Supply Current
Standby Current
2
(5)
ISB
ILI
ILO
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
0
10
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
VIL
–1
VCC x 0.3
VCC + 0.5
0.4
VIH
VOL1
VIL
Input High Voltage
VCC x 0.7
V
Output Low Voltage
Input Low Voltage (VCLK)
Input High Voltage (VCLK)
VCC = 3.0 V, IOL = 3 mA
V
V
CC ≥ 2.7 V
0.8
V
VIH
2.0
V
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1 V to V + 1 V.
CC
(5) Standby Current, I = 0 µA (<900 nA).
SB
Doc. No. 1032, Rev. L
2
CAT24C21
Units
A.C. CHARACTERISTICS
V
= 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.
CC
Symbol
Parameter
Min
Max
Transmit-only Mode
TVAA
TVHIGH
TVLOW
TVHZ
Output valid from VCLK
0.5
µs
µs
µs
µs
ns
VCLK high
0.6
1.3
VCLK low
Mode transition
Transmit-only power-up
0.5
TVPU
0
Read & Write Cycle Limits
FSCL
TI(1)
tAA
Clock Frequency
400
100
1
kHz
ns
Noise Suppression Time Constant at SCL,
SDA Inputs
SCL Low to SDA Data Out and ACK Out
µs
Time the Bus Must be Free Before a New
Transmission Can Start
(1)
tBUF
1.2
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
0.6
1.2
0.6
0.6
0
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
tHIGH
Clock High Period
tSU:STA
tHD:DAT
tSU:DAT
Start Condition Setup Time
Data In Hold Time
Data In Setup Time
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.3
(1)
tF
300
tSU:STO
tDH
Power-Up Timing(1)(2)
tPUR Power-up to Read Operation
tPUW Power-up to Write Operation
Write Cycle Limits
tWR Write Cycle Time
0.6
100
1
1
ms
ms
5
ms
circuits are disabled, SDA is allowed to remain high, and
the device does not respond to its slave address.
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/
erase cycle. During the write cycle, the bus interface
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1032, Rev. L
3
CAT24C21
TRANSMIT-ONLY MODE: (DDC1)
PIN DESCRIPTION
Upon power-up, the CAT24C21 will output valid data
only after it has been initialized. During initialization,
data will not be available until after the first nine clocks
aresenttothedevice(Figure2).Thestartingaddressfor
the transmit-only mode can be determined during
initialization. If the SDA pin is high during the first eight
clocks, the starting address will be 7FH. If the SDA pin
is low during the first eight clocks, the starting address
willbe00H.Duringtheninthclock,SDAwillbeinthehigh
impedance state.
The SCL serial clock input pin is used to clock all data
transfers into or out of the device when in the
bi-directional mode.
TheSDAbi-directionalserialdata/addresspinisusedto
transfer data into and out of the device. The SDA pin is
an open drain output and can be wire-ORed with other
open drain or open collector outputs.
FUNCTIONAL DESCRIPTION
TheCAT24C21hastwomodesofoperation:thetransmit-
only mode and the bi-directional mode. There is a
separate 2-wire protocol to support each mode, each
having a separate clock input (VCLK and SCL
respectively) and both modes sharing a common bi-
directional data line (SDA). The CAT24C21 enters the
transmit-onlymodeuponpowerupandbeginsoutputting
data on the SDA pin with each clock signal on the VCLK
pin. The device will remain in the transmit-only mode
until there is a valid HIGH to LOW transition on the SCL
pin, when it will switch to the bi-directional mode (Figure
1). Once in the bi-directinal mode, the only way to return
to the transmit-only mode is by powering down the
device.
Dataistransmittedin8bitwordswiththemostsignificant
bit first, followed by a 9th 'don't care' bit which will be in
thehighimpedancestate(Figure3). TheCAT24C21will
continuouslysequencethroughtheentirememoryarray
as long as VCLK is present and no falling edges on SCL
are detected. When the maximum address (7FH) is
reached,addressingwillwraparoundtothezerolocation
(00H) and transmitting will continue. The bi-directional
mode clock (SCL) pin must be held high for the device
to remain in the transmit-only mode.
The VCLK serial clock input pin is used to clock data out
of the device when in transmit-only mode. When held
low, in bi-directional mode, it will inhibit write operations.
Figure 1. Mode Transition
Transmit-Only Mode
Bi-Directional Mode
SCL
T
VHZ
SDA
VCLK
Figure 2. Device Initialization for Transmit-only Mode
SCL
SDA
SDA at high impedance for 9 clock cycles
Bit8
Bit7 Bit6 Bit5 Bit4
VCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
VPU
T
VAA
Doc. No. 1032, Rev. L
4
CAT24C21
STOP Condition
BI-DIRECTIONAL MODE (DDC2)
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
ThefollowingdefinesthefeaturesoftheI2Cbusprotocol
in bi-directional mode (Figure 4):
(1) Data transfer may be initiated only when the bus is
not busy.
Device Addressing
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24C21 (see Fig. 8). The next three
significant bits are "don't care". The last bit of the slave
address specifies whether a Read or Write operation is
to be performed. When this bit is set to 1, a Read
operationisselected,andwhensetto0,aWriteoperation
is selected.
When in the bi-directional mode, all inputs to the VCLK
pin are ignored, except when a logic high is required to
enable write capability.
START Condition
TheSTARTcondition(Figure6)precedesallcommands
tothedevice,andisdefinedasaHIGHtoLOWtransition
ofSDAwhenSCLisHIGH. TheCAT24C21monitorsthe
SDA and SCL lines and will not respond until this
condition is met.
After the Master sends a START condition and the slave
address byte, the CAT24C21 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24C21 then performs a Read or Write operation
depending on the state of the R/W bit.
Figure 3. Transmit-only Mode
SCL must remain high for transmit-only mode
SCL
Bit8
(MSB)
Bit1
Don't
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit8
Bit7
SDA
VCLK
(LSB) Care
T
T
VLOW
VHIGH
Doc. No. 1032, Rev. L
5
CAT24C21
Acknowledge
Write Operations
After a successful data transfer, each receiving device is
required to generate an acknowledge (ACK). The
acknowledging device pulls down the SDA line during the
ninth clock cycle, signaling that it has received the 8 bits of
data (Figure 7).
VCLK must be held high in order to program the device.
This applies to byte write and page write operation.
Once the device is in its self-timed program cycle,
VCLK can go low and not affect programming.
Byte Write
The CAT24C21 responds with an ACK after receiving a
START condition and its slave address. If the device has
been selected along with a write operation, it responds
with an ACK after receiving each 8-bit byte.
In the Byte Write mode (Figure 9), the Master device
sends the START condition and the slave address
information (with the R/W bit set to zero) to the Slave
device. After the Slave generates an ACK, the Master
sends the byte address that is to be written into the
addresspointeroftheCAT24C21.Afterreceivinganother
ACK from the Slave, the Master device transmits the
data byte to be written into the addressed memory
location. The CAT24C21 acknowledges once more and
the Master generates the STOP condition, at which time
the device begins its internal programming cycle to
nonvolatile memory (Figure 5). While this internal cycle
is in progress, the device will not respond to any request
from the Master device.
When the CAT24C21 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an ACK. Once it receives this ACK, the CAT24C21
will continue to transmit data. If no ACK is sent by the
Master, the device terminates data transmission and
waits for a STOP condition.
Figure 4. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 5. Write Cycle Timing
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc. No. 1032, Rev. L
6
CAT24C21
Page Write
Once all sixteen bytes are received and the STOP
condition has been sent by the Master, the internal
programmingcyclebegins.Atthispointallreceiveddata
is written to the CAT24C21 in a single write cycle.
The CAT24C21 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation (Figure 10) is initiated in the same
manner as the Byte Write operation, however instead of
terminating after the initial word is transmitted, the
Master is allowed to send up to fifteen additional bytes.
AftereachbytehasbeentransmittedtheCAT24C21will
respond with an ACK, and internally increment the low
order address bits by one. The high order bits remain
unchanged.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT24C21 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24C21 is still busy with
the write operation, no ACK will be returned. If the
CAT24C21 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
If the Master transmits more than sixteen bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
Figure 6. Start/Stop Timing
SDA
SCL
START Bit
STOP Bit
Figure 7. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 8. Slave Address Bits
1
0
1
0
X
X
X
R/W
Doc. No. 1032, Rev. L
7
CAT24C21
Write Protection
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation (Figure 12). The Master device first performs
a ‘dummy’ write operation by sending the START
condition,slaveaddressandbyteaddressofthelocation
itwishestoread.AftertheCAT24C21acknowledgesthe
word address, the Master device resends the START
condition and the slave address, this time with the R/W
bit set to one. The CAT24C21 then responds with its
ACK and sends the 8-bit byte requested. The master
device does not send an ACK but will generate a STOP
condition.
When the VCLK pin is connected to GND and the
CAT24C21 is in the bi-directional mode, the entire
memory is protected and becomes "read only".
Read Operations
TheREADoperationfortheCAT24C21isinitiatedinthe
same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
Sequential Read
The CAT24C21’s address counter contains the address
of the last byte accessed, incremented by one. In other
words,ifthelastREADorWRITEaccesswastoaddress
N, the READ immediately following would access data
from address N + 1 (Figure 11). If N = 127, then the
counter will 'wrap around' to address 0 and continue to
clock out data.
The Sequential READ operation (Figure 13) can be
initiated by either the Immediate Address READ or the
Selective READ operation. After the CAT24C21 sends
the first 8-bit byte, the Master responds with an ACK,
which tells the Slave that more data is being requested.
The CAT24C21 will continue to output an 8-bit byte for
each ACK sent by the Master. The entire memory
content can thus be read out sequentially. If the end of
memory is reached in the process, then addressing will
'wrap-around' to the beginning of memory. Data output
will stop when the Master fails to acknowledge and
sends a STOP condition.
Figure 9. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
* * *
*
A
C
K
A
C
K
A
C
K
Figure 10. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
* * *
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
n
MAX
= 7FH
P = 15 for CAT24WC21
* = Don't care
Doc. No. 1032, Rev. L
8
CAT24C21
Figure 11. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
* * *
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8
th Bit
DATA OUT
NO ACK
STOP
Figure 12. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
* * *
*
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 13. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1032, Rev. L
9
CAT24C21
ORDERING INFORMATION
Prefix
Device #
Suffix
24C21
CAT
J
X
TE13
Temperature Range
Blank = Industrial (-40 to 85 C)
E = Extended (-40 to 125 C)*
Product Number
Tape & Reel
TE13: 2000/Reel
Optional
Company ID
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
RD4: TDFN (3mm x 3mm)
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
ZD4: TDFN (3mm x 3mm, Lead free, Halogen free)
*available upon request
Notes:
(1) The device used in the above example is a CAT24C21J-TE13 (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
REVISION HISTORY
Date
Rev.
Reason
9/29/2003
H
Replaced Block Diagram with Functional Symbol
Eliminated commercial temperature range
Updated marking
10/15/2003
I
Added TDFN package
Updated Pin Descriptions
Updated DC Operating Characteristics
Updated AC Characateristics
Updated Byte Write Timing Figure
Updated Page Write Timing Figure
Updated Immediate Address Read Timing Figure
Updated Reliability Characteristics
Updated D.C. Operating Characteristics
Updated Capacitance
10/22/2003
J
10/24/2003
11/12/2003
K
L
Formatting Change
Corrected DC Operating Characteristics
Corrected AC Characteristics
Deleted Capacitance table
Doc. No. 1032, Rev. L
10
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
I2C is a trademark of Philips.
DDC, DDC1, DDC2 and VESA are trademarks of the Video Electronics Standards Association.
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1032
Revison:
Issue date:
Type:
L
11/13/03
Final
Fax: 408.542.1200
www.catalyst-semiconductor.com
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