CAT24C23LIT3 [CATALYST]
32-Kb I2C CMOS Serial EEPROM; 32 KB I2C CMOS串行EEPROM
| 型号： | CAT24C23LIT3 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 32-Kb I2C CMOS Serial EEPROM |
| 文件： | 总18页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
■ Supports Standard and Fast I2C Protocol
■ 1.8 V to 5.5 V Supply Voltage Range
■ 32-Byte Page Write Buffer
The CAT24C32 is a 32-Kb CMOS Serial EEPROM
devices, internally organized as 128 pages of 32 bytes
each.
It features a 32-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
■ Hardware Write Protection for entire memory
■ Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
External address pins make it possible to address up to
eight CAT24C32 devices on the same bus.
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Industrial temperature range
■ RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
TDFN packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (W)
TSSOP (Y)
V
CC
TDFN (ZD2, VP2)
A
1
8
V
CC
0
SCL
A
2
3
4
7
6
5
WP
1
2
A
SCL
SDA
A , A , A
CAT24C32
SDA
2
1
0
V
SS
For the location of Pin 1, please consult the
corresponding package drawing.
WP
PIN FUNCTIONS
V
SS
A0, A1, A2
SDA
SCL
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
WP
VCC
* The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu
pre-plated lead frames.
VSS
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
1
CAT24C32
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
(4)
NEND
TDR
Endurance
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, f= 400 kHz
1
mA
ICCW
ISB
Write Current
Write, f= 400 kHz
1
mA
All I/O Pins at GND or VCC
μA
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
1
1
IL
Pin at GND or VCC
μA
V
VIL
VIH
-0.5
VCC x 0.3
VCC x 0.7 VCC + 0.5
V
VOL1
VOL2
0.4
0.2
V
CC 2.5 V, I= 3.0 mA
VCC < 2.5 V, I= 1.0 mA
V
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Conditions
VIN = 0 V
VIN = 0 V
VIN < VIH
VIN > VIH
Max
8
Units
pF
(3)
CIN
SDA I/O Pin Capacitance
(3)
CIN
IWP
Input Capacitance (other pins)
WP Input Current
6
pF
(5)
100
1
μA
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
© 2007 by Catalyst Semiconductor, Inc.
Doc. No. 1101, Rev. G
2
Characteristics subject to change without notice
CAT24C32
A.C. CHARACTERISTICS(1)
VCC = 1.8 V to 5.5 V, T= -40°C to 85°C.
Standard
Fast
Symbol
Parameter
Max
Max
Units
FSCL
Clock Frequency
100
400
kHz
tHD:STA
tLOW
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
ns
ns
μs
μs
ms
ms
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
4.7
0
Data In Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
1000
300
300
300
(2)
tF
tSU:STO
tBUF
4
0.6
1.3
4.7
tAA
3.5
0.9
tDH
100
100
Ti(2)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
tSU:WP
tHD:WP
tWR
0
0
WP Hold Time
2.5
2.5
Write Cycle Time
5
1
5
1
(2, 3)
tPU
Power-up to Ready Mode
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
50 ns
Input Rise and Fall Times
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1101, Rev. G
3
CAT24C32
POWER-ON RESET (POR)
FUNCTIONAL DESCRIPTION
Each CAT24C32 incorporates Power-On Reset (POR)
circuitrywhichprotectstheinternallogicagainstpowering
up in the wrong state. The device will power up into
Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level. This bi-directional POR
behavior protects the device against ‘brown-out’ failure
following a temporary loss of power.
The CAT24C32 supports the Inter-Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a
Master device, which provides the clock and directs bus
traffic, and Slave devices which execute requests. The
CAT24C32 operates as a Slave device. Both Master
and Slave can transmit or receive, but only the Master
can assign those roles.
2
The 2-wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull-up resistors. The
Master provides the clock to the SCLline, and either the
MasterortheSlavesdrivetheSDAline.A‘0’istransmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics). During data transfer,
SDA must remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 1). The START consists of a
HIGHtoLOWSDAtransition,whileSCLisHIGH.Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW
to HIGH SDA transition, while SCL is HIGH.
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave address.
FortheCAT24C32,thefirstfourbitsoftheSlaveaddress
are set to 1010 (Ah); the next three bits, A2, A1 and A0
must match the logic state of the similarly named input
pins. The R/W bit tells the Slave whether the Master
intends to read (1) or write (0) data (Figure 2).
SDA: The Serial Data I/O pin accepts input data and
delivers output data. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device ad-
dress that must be matched by the corresponding Slave
address bits. The Address inputs are hard-wired HIGH
or LOW allowing for up to eight devices to be used
(cascaded) on the same bus. When left floating, these
pins are pulled LOW internally.
Acknowledge
During the 9th clock cycle following every byte sent to
the bus, the transmitter releases the SDA line, allow-
ing the receiver to respond. The receiver then either
acknowledges (ACK) by pulling SDA LOW, or does not
acknowledge(NoACK)bylettingSDAstayHIGH(Figure
3). Bus timing is illustrated in Figure 4.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin
is pulled LOW internally.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
4
CAT24C32
SCL
SDA
START
STOP
CONDITION
CONDITION
Figure 2. Slave Address Bits
1
0
1
0
A
A
A
0
R/W
2
1
DEVICE ADDRESS
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
t
BUF
t
t
AA
DH
SDA OUT
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1101, Rev. G
5
CAT24C32
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave ad-
dress with the R/W bit set to ‘0’. The Master then sends
two address bytes and a data byte and concludes the
session by creating a STOP condition on the bus. The
Slave responds with ACK after every byte sent by the
Master (Figure 5). The STOP starts the internal Write
cycle, and while this operation is in progress (tWR), the
SDAoutput is tri-stated and the Slave does not acknowl-
edge the Master (Figure 6).
Page Write
The Byte Write operation can be expanded to Page
Write, by sending more than one data byte to the Slave
before issuing the STOP condition (Figure 7). Up to 32
distinct data bytes can be loaded into the internal Page
Write Buffer starting at the address provided by the
Master. The page address is latched, and as long as the
Master keeps sending data, the internal byte address is
incremented up to the end of page, where it then wraps
around(withinthepage).Newdatacanthereforereplace
data loaded earlier. Following the STOP, data loaded
during the Page Write session will be written to memory
in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress,
the Slave will not acknowledge the Master. This feature
enables the Master to immediately follow-up with a new
Read or Write request, rather than wait for the maximum
specified Write time (tWR) to elapse. Upon receiving a
NoACK response from the Slave, the Master simply re-
peats the request until the Slave responds with ACK.
Hardware Write Protection
WiththeWPpinheldHIGH,theentirememoryisprotected
against Write operations. If the WP pin is left floating or
isgrounded, ithasnoimpactontheWriteoperation.The
state of the WP pin is strobed on the last falling edge
of SCL immediately preceding the 1st data byte (Figure
8). If the WP pin is HIGH during the strobe interval, the
Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24C32 is shipped erased, i.e., all bytes are
FFh.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
6
CAT24C32
Figure 5. Byte Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
O
P
ADDRESS
BYTE
DATA
BYTE
DATA
BYTE
SLAVE
ADDRESS
a
÷ a
a
÷ a
d ÷ d
7 0
15
8
7
0
S
P
* * * *
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
* a ÷ a are don't care bits.
15 12
Figure 6. Write Cycle Timing
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
T
O
P
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
SLAVE
ADDRESS
ADDRESS
BYTE
ADDRESS
BYTE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
n = 1
P ≤ 31
Figure 8. WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
a
a
d
7
d
0
SDA
WP
7
0
t
SU:WP
t
HD:WP
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1101, Rev. G
7
CAT24C32
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave ad-
dresswiththeR/W bitsetto‘1’. TheSlaverespondswith
ACK and starts shifting out data residing at the current
address. After receiving the data, the Master responds
with NoACK and terminates the session by creating a
STOP condition on the bus (Figure 9). The Slave then
returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address
register. This is done by starting a Byte Write sequence,
whereby the Master creates a START condition, then
broadcasts a Slave address with the R/W bit set to ‘0’
and then sends two address bytes to the Slave. Rather
than completing the Byte Write sequence by sending
data, the Master then creates a START condition and
broadcasts a Slave address with the R/W bit set to ‘1’.
TheSlaverespondswithACKaftereverybytesentbythe
Master and then sends out data residing at the selected
address. After receiving the data, the Master responds
withNoACKandthenterminatesthesessionbycreating
a STOP condition on the bus (Figure 10).
Sequential Read
If, after receiving data sent by the Slave, the Master
respondswithACK,thentheSlavewillcontinuetransmit-
ting until the Master responds with NoACK followed by
STOP (Figure 11). During Sequential Read the internal
byte address is automatically incremented up to the end
of memory, where it then wraps around to the beginning
of memory.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
8
CAT24C32
Figure 9. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10. Selective Read Sequence
N
O
S
A
C
K
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
T
A
R
T
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
DATA
BYTE
Figure 11. Sequential Read Sequence
N
O
BUS ACTIVITY:
SLAVE
S
A
C
K
A
C
K
A
C
K
A
C
K
T
O
P
MASTER
ADDRESS
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1101, Rev. G
9
CAT24C32
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
4.57
0.38
3.05
0.36
1.14
9.02
7.62
6.09
3.81
0.56
1.77
10.16
8.25
7.11
0.46
b2
D
E
7.87
6.35
E1
e
2.54 BSC
eB
L
7.87
0.115
9.65
0.150
0.130
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC Standard MS001.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
10
CAT24C32
8-LEAD 150 MIL WIDE SOIC (W)
E1
E
h x 45
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
0.10
1.35
0.33
0.19
4.80
5.80
3.80
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
θ1
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-012 dimensions.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1101, Rev. G
11
CAT24C32
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
θ
1
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MO-153.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
12
CAT24C32
8-PAD TDFN 3X4.9 PACKAGE (ZD2)
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.02
0.55
0.20 R E F
0.30
0.25
2.90
0.90
4.80
0.90
0.35
3.10
1.10
5.00
1.10
D
3.00
D2
E
1.00
4.90
E 2
e
1.00
0.65 TY P
0.60
L
0.50
0.70
Notes:
1. All dimensions are in millimeters. Angles in degree.
2. Complies with JEDEC MO-229.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1101, Rev. G
13
CAT24C32
8-LEAD TDFN 2x3 (VP2)
A
E
PIN 1 INDEX AREA
A1
D
D2
A2
A3
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
0.02
0.55
0.20 REF
0.25
2.00
1.40
3.00
1.30
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
D
D2
E
E2
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
PIN 1 ID
L
E2
e
L
0.50 TYP
0.30
0.20
0.40
b
e
3 x e
Notes:
1. All dimensions are in millimeters, angles in degrees.
2. Complies with JEDEC Standard MO-229.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
14
CAT24C32
Prefix
Device #
24C32
Suffix
CAT
Y
I
–
G
T3
Company ID Product Number
Temperature Range
I = Industrial (-40°C to +85°C)
T: Tape & Reel
2: 2000/Reel
3: 3000/Reel
24C32
Package
L: PDIP
Lead Finish
G: NiPdAu
W: SOIC, JEDEC
Y: TSSOP
ZD2: TDFN (3x4.9)(5)
VP2: TDFN (2x3)
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu on pre-plated (PPF) lead frames.
(3) The device used in the above example is a CAT24C32YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(5) TDFN, ZD2 is only available in 2000 pcs/reel, i.e., CAT24C32ZD2I-T2.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1101, Rev. G
15
CAT24C32
Date
Revision Comments
10/07/05
11/15/05
A
B
Initial Issue
Update Ordering Information
Add Tape and Reel Specifications
02/02/06
08/23/06
C
D
Update Ordering Information
Updated device description, supporting text and figures, package outlines, package
marking and ordering information.
Updated and re-formatted D.C. Characteristics presentation.
Updated and re-formatted A.C. Characteristics presentation to reflect
Standard (100 kHz) and Fast (400 kHz) operation over the full voltage range.
09/08/06
02/12/07
03/20/07
F
Remove Package Markings
UpdateTDFN 8 Lead (3x4.9mm) package
Add TDFN 8 Lead (2x3mm) package
G
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1101, Rev. G
16
CAT24C32
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory ™, DPP ™, EZDim ™, MiniPot™, and Quad-Mode™
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RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
© 2007 by Catalyst Semiconductor, Inc.
Doc No. 1101, Rev. G
17
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Publication #: 1101
Revison:
G
Issue date:
03/20/07
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