CAT24C44GLA [CATALYST]
Non-Volatile SRAM, 16X16, 375ns, CMOS, PDIP8, GREEN, PLASTIC, DIP-8;
| 型号： | CAT24C44GLA |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Non-Volatile SRAM, 16X16, 375ns, CMOS, PDIP8, GREEN, PLASTIC, DIP-8 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C44
256-Bit Serial Nonvolatile CMOS Static RAM
FEATURES
■ Single 5V Supply
■ JEDEC Standard Pinouts:
–8-pin DIP
■ Infinite EEPROM to RAM Recall
■ CMOS and TTL Compatible I/O
–8-pin SOIC
■ 100,000 Program/Erase Cycles (EEPROM)
■ Auto Recall on Power-up
■ Low CMOS Power Consumption:
–Active: 3 mA Max.
–Standby: 30 µA Max.
■ Commercial, Industrial and Automotive
Temperature Ranges
■ Power Up/Down Protection
■ 10 Year Data Retention
■ "Green" Package Options Available
DESCRIPTION
store protection circuitry prohibits STORE operations
when VCC is less than 3.5V (typical) ensuring EEPROM
data integrity.
The CAT24C44 Serial NVRAM is a 256-bit nonvolatile
memory organized as 16 words x 16 bits. The high
speed Static RAM array is bit for bit backed up by a
nonvolatile EEPROM array which allows for easy trans-
fer of data from RAM array to EEPROM (STORE) and
from EEPROM to RAM (RECALL). STORE operations
are completed in 10ms max. and RECALL operations
typically within 1.5µs. The CAT24C44 features unlim-
ited RAM write operations either through external RAM
writes or internal recalls from EEPROM. Internal false
The CAT24C44 is manufactured using Catalyst’s ad-
vancedCMOSfloatinggatetechnology.Itisdesignedto
endure 100,000 program/erase cycles (EEPROM) and
has a data retention of 10 years. The device is available
in JEDEC approved 8-pin plastic DIP and SOIC pack-
ages.
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name
SK
Function
Serial Clock
Serial Input
Serial Data Output
Chip Enable
Recall
DIP Package (P, L, GL)
SOIC Package (S, V, GV)
DI
1
2
3
4
8
7
6
5
CE
SK
DI
1
2
3
4
8
7
6
5
V
CE
V
CC
STORE
CC
STORE SK
RECALL DI
DO
RECALL
CE
DO
V
DO
V
SS
SS
RECALL
STORE
VCC
Store
+5V
VSS
Ground
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1083, Rev. R
1
CAT24C44
BLOCK DIAGRAM
EEPROM ARRAY
RECALL
ROW
DECODE
STATIC RAM
ARRAY
STORE
STORE
CONTROL
LOGIC
256-BIT
RECALL
CE
DI
INSTRUCTION
REGISTER
COLUMN
DECODE
DO
SK
V
V
CC
SS
INSTRUCTION
DECODE
4-BIT
COUNTER
MODE SELECTION(1)(2)
Software
Write Enable Previous Recall
Mode
STORE
RECALL
Instruction
Latch
Latch
Hardware Recall(3)
Software Recall
Hardware Store(3)
Software Store
X = Don’t Care
1
1
0
1
0
1
1
1
NOP
RCL
NOP
STO
X
X
X
X
SET
SET
TRUE
TRUE
POWER-UP TIMING(4)
Symbol
Parameter
Min.
0.5
Max.
0.005
200
5
Units
VCCSR
tpur
VCC Slew Rate
V/m
µs
Power-Up to Read Operations
tpuw
Power-Up to Write or Store Operation
ms
Note:
(1) The store operation has priority over all the other operations.
(2) The store operation is inhibited when V is below ≈ 3.5V.
CC
(3) NOP designates that the device is not currently executing an instruction.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
Doc. No. 1083, Rev. R
CAT24C44
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ............. –2.0 to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100,000
10
Typ.
Max.
Units
Cycles/Byte
Years
(1)
NEND
(1)
TDR
Data Retention
ESD Susceptibility
Latch-up
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
= 5V ±10%, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Unit
Conditions
ICCO
Current Consumption (Operating)
3
mA
Inputs = 5.5V, TA = 0°C
All Outputs Unloaded
ISB
ILI
Current Consumption (Standby)
Input Current
30
2
µA
µA
µA
V
CE = VIL
0 ≤ VIN ≤ 5.5V
0 ≤ VOUT ≤ 5.5V
ILO
VIH
VIL
VOH
VOL
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
10
2
0
VCC
0.8
V
2.4
V
IOH = –2mA
0.4
V
IOL = 4.2mA
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Parameter
Max.
Unit
pF
Conditions
VI/O = 0V
VIN = 0V
(1)
CI/O
Input/Output Capacitance
Input Capacitance
10
6
(1)
CIN
pF
Note:
(1) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1083, Rev. R
3
CAT24C44
A.C. CHARACTERISTICS
V
CC
= 5V ±10%, unless otherwise specified.
Symbol
FSK
tSKH
tSKL
tDS
Parameter
SK Frequency
Min.
DC
Max.
Units
MHz
ns
Conditions
1
SK Positive Pulse Width
SK Negative Pulse Width
Data Setup Time
400
400
400
80
ns
CL = 100pF + 1TTL gate
VOH = 2.2V, VOL = 0.65V
VIH = 2.2V, VIL = 0.65V
ns
tDH
Data Hold Time
ns
tPD
SK Data Valid Time
CE Disable Time
375
1
ns
Input rise and fall times = 10ns
tZ
µs
tCES
tCEH
tCDS
CE Enable Setup Time
CE Enable Hold Time
CE De-Select Time
800
400
800
ns
ns
ns
A.C. CHARACTERISTICS, Store Cycle
= 5V ±10%, unless otherwise specified.
V
CC
Limits
Symbol
tST
Parameter
Store Time
Min.
Max.
Units
ms
Conditions
10
CL = 100pF + 1TTL gate
VOH = 2.2V, VOL = 0.65V
VIH = 2.2V, VIL = 0.65V
tSTP
Store Pulse Width
Store Disable Time
200
ns
tSTZ
100
ns
A.C. CHARACTERISTICS, Recall Cycle
= 5V ±10%, unless otherwise specified.
V
CC
Symbol
tRCC
Parameter
Min.
2.5
Max.
Units
µs
Conditions
Recall Cycle Time
Recall Pulse Width
Recall Disable Time
Recall Enable Time
Recall Data Access Time
tRCP
500
ns
CL = 100pF + 1TTL gate
VOH = 2.2V, VOL = 0.65V
VIH = 2.2V, VIL = 0.65V
tRCZ
500
1.5
ns
tORC
10
ns
tARC
µs
INSTRUCTION SET
Format
Start Bit Address OP Code
Instruction
WRDS
STO
Operation
1
1
1
1
1
1
XXXX
XXXX
AAAA
XXXX
XXXX
AAAA
0 0 0
0 0 1
0 1 1
1 0 0
1 0 1
1 1 X
Reset Write Enable Latch (Disables, Writes and Stores)
Store RAM Data in EEPROM
WRITE
WREN
RCL
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables, Writes and Stores)
Recall EEPROM Data into RAM
READ
Read Data From RAM Address AAAA
X = Don’t care
A = Address bit
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
Doc. No. 1083, Rev. R
CAT24C44
from the device: If the CE pin is prematurely deselected
while shifting in an instruction, that instruction will not be
executed,andtheshiftregisterinternaltotheCAT24C44
will be cleared. If there are more than or less than 16
clocks during a memory data transfer, an improper data
transfer will result. The SK clock is completely static
allowing the user to stop the clock and restart it to
resume shifting of data.
DEVICE OPERATION
The CAT24C44 is intended for use with standard micro-
processors.TheCAT24C44isorganizedas16registers
by 16 bits. Seven 8-bit instructions control the device’s
operating modes, the RAM reading and writing, and the
EEPROM storing and recalling. It is also possible to
control the EEPROM store and recall functions in hard-
warewiththeSTOREandRECALLpins.TheCAT24C44
operates on a single 5V supply and will generate, on
chip,thehighvoltagerequiredduringaRAMtoEEPROM
storing operation.
Read
Upon receiving a start bit, 4 address bits, and the 3-bit
read command (clocked into the DI pin), the DO pin of
theCAT24C44willcomeoutofthehighimpedancestate
and the 16 bits of data, located at the address specified
in the instructions, will be clocked out of the device.
When clocking data from the device, the first bit clocked
out (DO) is timed from the falling edge of the 8th clock,
all succeeding bits (D1–D15) are timed from the rising
edge of the clock.
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin remains in a high impedance state except when
outputting data from the device. The CE (Chip Enable)
pin must remain high during the entire data transfer.
The format for all instructions sent to the CAT24C44 is
a logical ‘1’ start bit, 4 address bits (data read or write
operations) or 4 “Don’t Care” bits (device mode opera-
tions), and a 3-bit op code (see Instruction Set). For data
write operations, the 8-bit instruction is followed by 16
bits of data. For data read instructions, DO will come out
of the high impedance state and enable 16 bits of data
to be clocked from the device. The 8th bit of the read
instruction is a “Don’t Care” bit. This is to eliminate any
bus contention that would occur in applications where
the DI and DO pins are tied together to form a common
DI/DO line. A word of caution while clocking data to and
Write
After receiving a start bit, 4 address bits, and the 3-bit
WRITE command, the 16-bit word is clocked into the
device for storage into the RAM memory location speci-
fied. The CE pin must remain high during the entire write
operation.
Figure 1. RAM Read Cycle Timing
CE
1
2
3
4
5
6
7
8
9
10
11
12
22
23
24
SK
DI
(1)
1
A
A
A
AX
1
1
HIGH-Z
DO
D
D
D
D
D
D
15
D
0
1
2
3
14
0
Figure 2. RAM Write Cycle Timing
CE
1
2
3
4
5
6
7
8
9
10
11
12
22
23
24
SK
1
A
A
A
A1
0
1
D
D
D
D
D
D
D
15
DI
0
1
2
3
13
14
Note:
(1) Bit 8 of READ instruction is “Don’t Care”.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1083, Rev. R
5
CAT24C44
WREN/WRDS
The WRDS (write/store disable) can be used to disable
all CAT24C44 programming functions, and will prevent
any accidental writing to the RAM, or storing to the
EEPROM.
The CAT24C44 powers up in the program disable state
(the“writeenablelatch”isreset).Anyprogrammingafter
power-up or after a WRDS (RAM write/EEPROM store
disable) instruction must first be preceded by the WREN
(RAM write/EEPROM store enable) instruction. Once
writing/storing is enabled, it will remain enabled until
power to the device is removed, the WRDS instruction is
sent, or an EEPROM store has been executed (STO).
Data can be read normally from the CAT24C44 regard-
less of the “write enable latch” status.
Figure 3. Read Cycle Timing
SK CYCLE #
6
7
8
9
10
11
SK
CE
V
IH
t
PD
DI
t
t
Z
PD
HIGH-Z
HIGH-Z
DO
D0
D1
Dn
Figure 4. Write Cycle Timing
1/F
SK
t
t
SKH
SKL
2
x
1
n
SK
CE
t
t
t
CDS
CES
CEH
t
t
DH
DS
DI
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
Doc. No. 1083, Rev. R
CAT24C44
RCL/RECALL
inadvertent store operations, the following conditions
must each be met before data can be transferred into
nonvolatile storage:
Data is transferred from the EEPROM data memory to
RAM by either sending the RCL instruction or by pulling
the RECALL input pin low. A recall operation must be
performed before the EEPROM store, or RAM write
operations can be executed. Either a hardware or soft-
ware recall operation will set the “previous recall” latch
internal to the CAT24C44.
• The “previous recall” latch must be set (either a
software or hardware recall operation).
• The “write enable” latch must be set (WREN
instruction issued).
POWER-ON RECALL
• STO instruction issued or STORE input low.
During the store operation, all other CAT24C44 func-
tions are inhibited. Upon completion of the store opera-
tion, the “write enable” latch is reset. The device also
providesfalsestoreprotectionwheneverVCC fallsbelow
a 3.5V level. If VCC falls below this level, the store
operation is disabled and the “write enable” latch is
reset.
The CAT24C44 has a power-on recall function that
transfers the EEPROM data to the RAM. After Power-
up, all functions are inhibited for at least 200ns (Tpur
)
from stable Vcc.
STO/STORE
Data in the RAM memory area is stored in the EEPROM
memory either by sending the STO instruction or by
pulling the STORE input pin low. As security against any
Figure 5. Recall Cycle Timing
t
RCC
t
RCP
RECALL
t
t
ARC
RCZ
HIGH-Z
DO
VALID DATA
t
ORC
UNDEFINED DATA
Figure 6. Hardware Store Cycle Timing
t
ST
t
STP
STORE
DO
t
STZ
HIGH-Z
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1083, Rev. R
7
CAT24C44
Figure 7. Non-Data Operations
CE
1
1
2
3
4
5
6
7
8
SK
DI
X
X
X
X
OP-CODE
ORDERING INFORMATION
Prefix
Device #
24C44
Suffix
CAT
S
I
-TE13
Optional
Company ID
Temperature Range
Blank = Commercial (0˚C to 70˚C)
Product
Number
Tape & Reel
I = Industrial (-40˚C to 85˚C)
A = Automotive (-40˚C to 105˚C)
E = Extended (-40˚C to 125˚C)
Package
P: PDIP
S: SOIC, JEDEC
L: PDIP (Lead-free, Halogen-free)
V: SOIC, JEDEC (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a CAT24C44SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8
Doc. No. 1083, Rev. R
REVISION HISTORY
Date
Revision Comments
04/17/2004
O
Add Lead Free Logo
Update Features
Update Pin Configuration
Update Block Diagram
Update Instruction Set
Update Device Operation
Update Ordering Information
Add Revision History
Update Rev Number
11/16/2004
P
Update Pin Configuration
Update Ordering Information
04/17/2004
08/03/2005
Q
R
Update Ordering Information
Update Pin Configuration
Update Reliability Characteristics
Update Ordering Information
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Publication #: 1083
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Revison:
R
Issue date:
08/03/05
相关型号：
CAT24C44GLI
IC 16 X 16 NON-VOLATILE SRAM, 375 ns, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8, Static RAM
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