CAT24FC01RD7I-TE13

更新时间:2024-10-30 02:20:14
品牌:CATALYST
描述:EEPROM, 128X8, Serial, CMOS, PDSO8, TDFN-8

CAT24FC01RD7I-TE13 概述

EEPROM, 128X8, Serial, CMOS, PDSO8, TDFN-8

CAT24FC01RD7I-TE13 数据手册

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CAT24FC01, CAT24FC02  
1-kb/2-kb I2C Serial EEPROM  
TM  
FEATURES  
400 kHz (2.5 V) and 100 kHz (1.7 V) I2C bus  
1,000,000 program/erase cycles  
100 year data retention  
compatible  
1.7 to 5.5 volt operation  
8-pin DIP, 8-pin SOIC, 8-pin TSSOP and TDFN  
packages  
Low power CMOS technology  
– zero standby current  
- “Green” package option available  
256 x 8 memory organization  
Hardware write protect  
16-byte page write buffer  
Industrial and extended temperature ranges  
Self-timed write cycle with auto-clear  
DESCRIPTION  
The CAT24FC01/2 features a 16-byte page write buffer.  
The device operates via the I2C bus serial interface and  
is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and  
TDFN packages.  
TheCAT24FC01/2isa1-kb/2-kbSerialCMOSEEPROM  
internally organized as 128/256 words of 8 bits each.  
Catalyst’s advanced CMOS technology substantially  
reduces device power requirements.  
PIN CONFIGURATION  
BLOCK DIAGRAM  
EXTERNAL LOAD  
DIP Package (P, L)  
SOIC Package (J, W)  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
ACK  
0
1
2
CC  
0
1
2
V
CC  
WP  
V
WP  
CC  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
V
SCL  
SDA  
SS  
SCL  
SDA  
V
V
SS  
SS  
START/STOP  
LOGIC  
SDA  
WP  
TSSOP Package (U, Y)  
1
2
3
4
8
7
6
5
A
0
1
2
V
CC  
WP  
E2PROM  
A
A
XDEC  
CONTROL  
LOGIC  
SCL  
SDA  
V
SS  
MSOP Package (R, Z)  
TDFN Package (RD4, ZD4)  
DATA IN STORAGE  
1
2
3
4
8
7
6
5
A0  
A1  
A2  
8
7
6
5
1
2
3
4
V
V
A0  
A1  
A2  
CC  
CC  
WP  
WP  
HIGH VOLTAGE/  
TIMING CONTROL  
SCL  
SDA  
SCL  
SDA  
V
SS  
V
SS  
SCL  
STATE COUNTERS  
SLAVE  
ADDRESS  
COMPARATORS  
A
0
A1  
A2  
PIN FUNCTIONS  
Pin Name  
Function  
A0, A1, A2  
SDA  
Device Address Inputs  
Serial Data/Address  
Serial Clock  
SCL  
WP  
Write Protect  
VCC  
1.7 V to 5.5 V Power Supply  
Ground  
* Catalyst Semiconductor is licensed by Philips Corporation to carry  
the I C Bus Protocol.  
2
VSS  
© 2003 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc No. 1066, Rev. B  
1
CAT24FC01, CAT24FC02  
Lead Soldering Temperature (10 seconds) ...... 300°C  
Output Short Circuit Current(2) ....................... 100 mA  
ABSOLUTE MAXIMUM RATINGS*  
Temperature Under Bias  
55°C to +125°C  
Storage Temperature....................... 65°C to +150°C  
*COMMENT  
Voltage on Any Pin with  
Stresses above those listed under Absolute Maximum Ratingsmay  
cause permanent damage to the device. These are stress ratings only,  
and functional operation of the device at these or any other conditions  
outsideofthoselistedintheoperationalsectionsofthisspecificationisnot  
implied. Exposure to any absolute maximum rating for extended periods  
Respect to Ground(1) ............2.0 V to VCC + 2.0 V  
VCC with Respect to Ground ............. 2.0 V to +7.0 V  
Package Power Dissipation  
Capability (TA = 25°C) .................................. 1.0 W  
may affect device performance and reliability.  
RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Reference Test Method  
Min  
Typ  
Max  
Units  
Cycles/Byte  
Years  
(3)  
NEND  
MIL-STD-883, Test Method 1033 1,000,000  
(3)  
TDR  
Data Retention  
MIL-STD-883, Test Method 1008  
100  
4000  
100  
(3)  
VZAP  
ESD Susceptibility MIL-STD-883, Test Method 3015  
Latch-up JEDEC Standard 17  
Volts  
(3)(4)  
ILTH  
mA  
D.C. OPERATING CHARACTERISTICS  
V
= 1.7 V to 5.5 V, unless otherwise specified.  
CC  
Symbol  
ICC  
Parameter  
Test Conditions  
fSCL = 100 kHz  
Min  
Typ  
1
Max  
Units  
mA  
mA  
µA  
Power Supply Current (Read)  
Power Supply Current (Write)  
Standby Current (VCC = 5.0 V)  
Input Leakage Current  
ICC  
fSCL = 100 kHz  
3
(5)  
ISB  
VIN = GND or VCC  
VIN = GND to VCC  
VOUT = GND to VCC  
0
ILI  
ILO  
1
µA  
Output Leakage Current  
Input Low Voltage  
1
µA  
VIL  
1  
VCC x 0.3  
VCC + 1.0  
V
V
V
V
VIH  
Input High Voltage  
VCC x 0.7  
VOL1  
VOL2  
Output Low Voltage (VCC = 3.0 V)  
Output Low Voltage (VCC = 1.7 V)  
IOL = 3 mA  
0.4  
0.5  
IOL = 1.5 mA  
CAPACITANCE T = 25°C, f = 400 kHz, V  
= 5 V  
CC  
A
Symbol  
Test  
Conditions  
VI/O = 0 V  
VIN = 0 V  
Min  
Typ  
Max  
8
Units  
pF  
(3)  
CI/O  
Input/Output Capacitance (SDA)  
Input Capacitance (other pins)  
(3)  
CIN  
6
pF  
Note:  
(1) The minimum DC input voltage is 0.5 V. During transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.  
CC  
CC  
(2) Output shorted for no more than one second. No more than one output shorted at a time.  
(3) This parameter is tested initially and after a design or process change that affects the parameter.  
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1.0 V to V + 1.0 V.  
CC  
(5) Standby Current, I = 0 µA (<900 nA).  
SB  
Doc. No. 1066, Rev. B  
2
CAT24FC01, CAT24FC02  
A.C. CHARACTERISTICS  
V
= 1.7 V to 5.5 V, unless otherwise specified.  
CC  
Read & Write Cycle Limits  
Symbol  
Parameter  
1.7 V - 5.5 V  
2.5 V - 5.5 V  
Min  
Max  
100  
100  
Min  
Max  
Units  
kHz  
ns  
FSCL  
TI(1)  
Clock Frequency  
400  
100  
Noise Suppression Time  
Constant at SCL, SDA Inputs  
tAA  
SCL Low to SDA Data Out  
and ACK Out  
3.5  
0.9  
µs  
µs  
(1)  
tBUF  
Time the Bus Must be Free Before  
a New Transmission Can Start  
4.7  
1.3  
tHD:STA  
tLOW  
Start Condition Hold Time  
Clock Low Period  
4
0.6  
1.3  
0.6  
0.6  
µs  
µs  
µs  
µs  
4.7  
4
tHIGH  
Clock High Period  
tSU:STA  
Start Condition Setup Time  
4.7  
(for a Repeated Start Condition)  
tHD:DAT  
tSU:DAT  
Data In Hold Time  
0
0
ns  
ns  
µs  
ns  
µs  
ns  
Data In Setup Time  
250  
100  
(1)  
tR  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
Stop Condition Setup Time  
Data Out Hold Time  
1
0.3  
(1)  
tF  
300  
300  
tSU:STO  
tDH  
4
0.6  
100  
100  
(1)(2)  
Power-Up Timing  
Symbol  
Parameter  
Min  
Min  
Typ  
Max  
1
Units  
ms  
tPUR  
tPUW  
Power-up to Read Operation  
Power-up to Write Operation  
1
ms  
Write Cycle Limits  
Symbol  
Parameter  
Typ  
Max  
Units  
tWR  
Write Cycle Time  
5
ms  
interface circuits are disabled, SDA is allowed to remain  
high, and the device does not respond to its slave  
address.  
The write cycle time is the time from a valid stop  
condition of a write sequence to the end of the internal  
program/erase cycle. During the write cycle, the bus  
Note:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
(2) t  
and t  
are the delays required from the time V is stable until the specified operation can be initiated.  
PUR  
PUW  
CC  
Doc No. 1066, Rev. B  
3
CAT24FC01, CAT24FC02  
alldatatransfersintooroutofthedevice. Thisisaninput  
pin.  
FUNCTIONAL DESCRIPTION  
The CAT24FC01/2 supports the I2C Bus data  
transmission protocol. This Inter-Integrated Circuit Bus  
protocol defines any device that sends data to the bus to  
be a transmitter and any device receiving data to be a  
receiver.DatatransferiscontrolledbytheMasterdevice  
which generates the serial clock and all START and  
STOP conditions for bus access. The CAT24FC01/2  
operates as a Slave device. Both the Master and Slave  
devicescanoperateaseithertransmitterorreceiver,but  
the Master device controls which mode is activated. A  
maximum of 8 devices may be connected to the bus as  
determinedbythedeviceaddressinputsA0,A1,andA2.  
SDA: Serial Data/Address  
The CAT24FC01/2 bidirectional serial data/address pin  
is used to transfer data into and out of the device. The  
SDA pin is an open drain output and can be wire-ORed  
with other open drain or open collector outputs.  
A0, A1, A2: Device Address Inputs  
Theseinputssetdeviceaddresswhencascadingmultiple  
devices. A maximum of eight devices can be cascaded  
when using the device.  
WP: Write Protect  
This input, when tied to GND, allows write operations to  
the entire memory. For CAT24FC01/2 when this pin is  
tied to VCC, the entire array of memory is write protected.  
When left floating, memory is unprotected.  
PIN DESCRIPTIONS  
SCL: Serial Clock  
The CAT24FC01/2 serial clock input pin is used to clock  
t
t
t
Figure 1. Bus Timing  
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
SU:STA  
HD:DAT  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
SDA IN  
BUF  
t
t
AA  
DH  
SDA OUT  
5020 FHD F03  
Figure 2. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
5020 FHD F04  
Figure 3. Start/Stop Timing  
SDA  
SCL  
START BIT  
STOP BIT  
5020 FHD F05  
Doc. No. 1066, Rev. B  
4
CAT24FC01, CAT24FC02  
I2C BUS PROTOCOL  
and define which device the Master is accessing. Up to  
eight CAT24FC01/2 may be individually addressed by  
the system. The last bit of the slave address specifies  
whether a Read or Write operation is to be performed.  
When this bit is set to 1, a Read operation is selected,  
and when set to 0, a Write operation is selected.  
The following defines the features of the I2C bus proto-  
col:  
(1) Data transfer may be initiated only when the bus is  
not busy.  
After the Master sends a START condition and the slave  
address byte, the CAT24FC01/2 monitors the bus and  
responds with an acknowledge (on the SDA line) when  
its address matches the transmitted slave address. The  
CAT24FC01/2 then performs a Read or a Write opera-  
tion depending on the state of the R/W bit.  
(2) During a data transfer, the data line must remain  
stable whenever the clock line is high. Any changes  
in the data line while the clock line is high will be  
interpreted as a START or STOP condition.  
START Condition  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
SDAwhenSCLisHIGH. TheCAT24FC01/2monitorthe  
SDA and SCL lines and will not respond until this  
condition is met.  
Acknowledge  
Afterasuccessfuldatatransfer, eachreceivingdeviceis  
requiredtogenerateanacknowledge.TheAcknowledg-  
ing device pulls down the SDA line during the ninth clock  
cycle, signaling that it received the 8 bits of data.  
STOP Condition  
The CAT24FC01/2 responds with an acknowledge after  
receivingaSTARTconditionanditsslaveaddress. Ifthe  
device has been selected along with a write operation,  
it responds with an acknowledge after receiving each  
byte.  
A LOW to HIGH transition of SDA when SCL is HIGH  
determinestheSTOPcondition.Alloperationsmustend  
with a STOP condition.  
DEVICE ADDRESSING  
When the CAT24FC01/2 begins a READ mode, it trans-  
mits 8 bits of data, releases the SDA line, and monitors  
the line for an acknowledge. Once it receives this ac-  
knowledge, the CAT24FC01/2 will continue to transmit  
data. IfnoacknowledgeissentbytheMaster, thedevice  
terminates data transmission and waits for a STOP  
condition.  
The Master begins a transmission by sending a START  
condition. The Master then sends the address of the  
particular slave device it is requesting. The four most  
significant bits of the 8-bit slave address are fixed as  
1010 for the CAT24FC01/2 (see Fig. 5). The next three  
significant bits (A2, A1, A0) are the device address bits  
Figure 4. Acknowledge Timing  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
Figure 5. Slave Address Bits  
1
0
1
0
A2  
A1  
A0 R/W  
Normal Read and Write  
DEVICE ADDRESS  
Doc No. 1066, Rev. B  
5
CAT24FC01, CAT24FC02  
Once all 16 bytes are received and the STOP condition  
has been sent by the Master, the internal programming  
cycle begins. At this point all received data is written to  
the CAT24FC01/2 in a single write cycle.  
WRITE OPERATIONS  
Byte Write  
In the Byte Write mode, the Master device sends the  
START condition and the slave address information  
(with the R/W bit set to zero) to the Slave device. After  
the Slave generates an acknowledge, the Master sends  
the byte address that is to be written into the address  
pointer of the CAT24FC01/2. After receiving another  
acknowledgefromtheSlave,theMasterdevicetransmits  
the data byte to be written into the addressed memory  
location. The CAT24FC01/2 acknowledges once more  
and the Master generates the STOP condition, at which  
time the device begins its internal programming to  
nonvolatile memory. While this internal cycle is in  
progress, thedevicewillnotrespondtoanyrequestfrom  
the Master device.  
Acknowledge Polling  
Thedisablingoftheinputscanbeusedtotakeadvantage  
of the typical write cycle time. Once the stop condition  
isissuedtoindicatetheendofthehostswriteoperation,  
the CAT24FC01/2 initiates the internal write cycle. ACK  
polling can be initiated immediately. This involves  
issuing the start condition followed by the slave address  
for a write operation. If the CAT24FC01/2 is still busy  
with the write operation, no ACK will be returned. If the  
CAT24FC01/2 has completed the write operation, an  
ACK will be returned and the host can then proceed with  
the next read or write operation.  
Page Write  
WRITE PROTECTION  
The CAT24FC01/2 writes up to 16 bytes of data in a  
single write cycle, using the Page Write operation. The  
Page Write operation is initiated in the same manner as  
theByteWriteoperation,howeverinsteadofterminating  
after the initial word is transmitted, the Master is allowed  
to send up to 15 additional bytes. After each byte has  
beentransmittedtheCAT24FC01/2willrespondwithan  
acknowledge, and internally increment the low order  
address bits by one. The high order bits remain  
unchanged.  
The CAT24FC01/2 is designed with a hardware protect  
pin that enables the user to protect the entire memory.  
Thehardware protection feature of the CAT24FC01/2 is  
designed into the part to provide added flexibility to the  
design engineers. The write protection feature of  
CAT24FC01/2 allows the user to protect against  
inadvertentprogrammingofthememoryarray.IftheWP  
pin is tied to Vcc, the entire memory array is protected  
and becomes read only. The entire memory becomes  
write protected regardless of whether the write protect  
register has been written or not. When WP pin is tied to  
Vcc, the user cannot program the write protect register.  
If the WP pin is left floating or tied to Vss, the device can  
be written into.  
If the Master transmits more than 16 bytes prior to  
sendingtheSTOPcondition,theaddresscounterwraps  
around, and previously transmitted data will be  
overwritten.  
Figure 6. Byte Write Timing  
S
T
S
A
R
T
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS  
DATA  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
5020 FHD F08  
Figure 7. Page Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
DATA n  
DATA n+1  
DATA n+P  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
5020 FHD F09  
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0  
Doc. No. 1066, Rev. B  
6
CAT24FC01, CAT24FC02  
Read Operations  
read. After the CAT24FC01/2 acknowledge the word  
address,theMasterdeviceresendstheSTARTcondition  
and the slave address, this time with the R/W bit set to  
one. The CAT24FC01/2 then responds with its  
acknowledge and sends the 8-bit byte requested. The  
master device does not send an acknowledge but will  
generate a STOP condition.  
The READ operation for the CAT24FC01/2 is initiated in  
the same manner as the write operation with the one  
exception that the R/W bit is set to a one. Three different  
READ operations are possible: Immediate Address  
READ, Selective READ and Sequential READ.  
Immediate Address Read  
Sequential Read  
The CAT24FC01/2s address counter contains the  
address of the last byte accessed, incremented by one.  
In other words, if the last READ or WRITE access was  
to address N, the READ immediately following would  
access data from address N + 1. If N = 255 for 24FC02,  
then the counter will wrap aroundto address 0 and  
continuetoclockoutdata.IfN=127fortheCAT24FC01,  
the counter will not wrap around. After the CAT24FC02  
receives its slave address information (with the R/W bit  
set to one), it issues an acknowledge, then transmits the  
8-bit byte requested. The master device does not send  
an acknowledge but will generate a STOP condition.  
The Sequential READ operation can be initiated by  
either the Immediate Address READ or Selective READ  
operations. After the CAT24FC01/2 sends the initial 8-  
bit data requested, the Master will respond with an  
acknowledge which tells the device it requires more  
data.TheCAT24FC01/2willcontinuetooutputabytefor  
each acknowledge sent by the Master. The operation  
willterminateoperationwhentheMasterfailstorespond  
with an acknowledge, thus sending the STOP condition.  
The data being transmitted from the CAT24FC01/2 is  
outputtedsequentiallywithdatafromaddressNfollowed  
by data from address N + 1. The READ operation  
address counter increments all of the CAT24FC01/2  
addressbitssothattheentirememoryarraycanberead  
duringoneoperation.Ifmorethanthe256bytesareread  
out, the counter will wrap aroundand continue to clock  
out data bytes.  
Selective Read  
Selective READ operations allow the Master device to  
select at random any memory location for a READ  
operation. The Master device first performs a dummy’  
write operation by sending the START condition, slave  
address and byte address of the location it wishes to  
Figure 8. Immediate Address Read Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
SDA LINE  
S
P
A
C
K
N
DATA  
O
A
C
K
SCL  
SDA  
8
9
8TH BIT  
DATA OUT  
NO ACK  
STOP  
Doc No. 1066, Rev. B  
7
CAT24FC01, CAT24FC02  
Figure 9. Selective Read Timing  
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
SLAVE  
ADDRESS  
SDA LINE  
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n  
A
C
K
Figure 10. Sequential Read Timing  
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
SDA LINE  
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1066, Rev. B  
8
CAT24FC01, CAT24FC02  
ORDERING INFORMATION  
Prefix  
Device #  
24FC02  
Suffix  
CAT  
J
X
I
TE13  
Optional  
Company ID  
Temperature Range  
I = Industri  
E = Extended (-40°C to +125°C)  
Tape & Reel  
TE13: 2000/Reel  
Product  
Number  
Package  
Operating Voltage  
Blank: 1.7V - 5.5V  
P: PDIP  
J: SOIC (JEDEC)  
R: MSOP  
U: TSSOP  
RD7: TDFN  
L: PDIP (Lead free, Halogen free)  
W: SOIC (JEDEC), (Lead free, Halogen free)  
Y: TSSOP (Lead free, Halogen free)  
Z: MSOP (Lead free, Halogen free)  
ZD7: TDFN (Lead free, Halogen free)  
Notes:  
(1) The device used in the above example is a 24FC02JI-TE13 (SOIC, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating Voltage, Tape & Reel)  
Doc No. 1066, Rev. B  
9
CAT24FC01, CAT24FC02  
REVISION HISTORY  
Date  
Rev.  
Reason  
11/18/2003  
12/9/2003  
A
B
Initial Issue  
Changed Industrial Temp to Ifrom Blankin ordering information  
Doc. No. 1066, Rev. B  
10  
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Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:  
DPP ™  
DPPs ™ AE2 ™  
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents  
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.  
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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE  
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Catalyst Semiconductor, Inc.  
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Preliminary  
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CAT24FC01RD7I-TE13 相关器件

型号 制造商 描述 价格 文档
CAT24FC01RE CATALYST EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8 获取价格
CAT24FC01RE-REV-E CATALYST EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8 获取价格
CAT24FC01RE-TE13 CATALYST CAT24FC01RE-TE13 获取价格
CAT24FC01RE-TE13REV-E CATALYST EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8 获取价格
CAT24FC01RETE13 CATALYST 1-kb I2C Serial EEPROM 获取价格
CAT24FC01RETE13REV-F CATALYST 1-kb I2C Serial EEPROM 获取价格
CAT24FC01RI CATALYST CAT24FC01RI 获取价格
CAT24FC01RI-REV-E CATALYST EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8 获取价格
CAT24FC01RI-REV-F CATALYST EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8 获取价格
CAT24FC01RI-TE13 CATALYST CAT24FC01RI-TE13 获取价格

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