CAT24FC16JI [CATALYST]
EEPROM, 2KX8, Serial, CMOS, PDSO8, SOIC-8;
| 型号： | CAT24FC16JI |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 2KX8, Serial, CMOS, PDSO8, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总11页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT24FC16
16-kb I2C Serial EEPROM
TM
FEATURES
I 400 kHz (2.5 V) and 100 kHz (1.8 V) I2C bus
I 1,000,000 program/erase cycles
I 100 year data retention
compatible
I 1.8 to 5.5 volt operation
I 8-pin DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin MSOP
and TDFN packages
I Low power CMOS technology
I 16-byte page write buffer
- “Green” package option available
I 256 x 8 memory organization
I Hardware write protect
I Industrial and extended temperature ranges
I Self-timed write cycle with auto-clear
DESCRIPTION
featuresa16-bytepagewritebuffer.Thedeviceoperates
via the I2C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin MSOP and TDFN
packages.
The CAT24FC16 is a 16-kb Serial CMOS EEPROM
internally organized as 2048 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC16
PIN CONFIGURATION
BLOCK DIAGRAM
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
D
OUT
DIP Package (P, L)
SOIC Package (J, W)
ACK
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
NC
NC
NC
V
V
NC
NC
NC
CC
CC
V
CC
WP
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
WP
V
SS
SCL
SDA
SCL
SDA
V
V
SS
SS
START/STOP
LOGIC
SDA
WP
E2PROM
XDEC
TSSOP Package (U, Y)
CONTROL
LOGIC
1
2
3
4
8
7
6
5
NC
NC
NC
V
CC
WP
SCL
SDA
DATA IN STORAGE
V
SS
HIGH VOLTAGE/
TIMING CONTROL
MSOP Package (R, Z)
TDFN Package (RD4, ZD4)
SCL
STATE COUNTERS
V
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
NC
NC
NC
CC
V
NC
NC
NC
CC
WP
SCL
SDA
WP
PIN FUNCTIONS
SCL
SDA
V
SS
Pin Name
NC
Function
No Connect
V
SS
SDA
SCL
Serial Data/Address
Serial Clock
WP
Write Protect
VCC
1.8 V to 5.5 V Power Supply
Ground
* Catalyst Semiconductor is licensed by Philips Corporation
VSS
2
to carry the I C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1054, Rev. G
1
CAT24FC16
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current(2) ....................... 100 mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
–55°C to +125°C
Storage Temperature....................... –65°C to +150°C
*COMMENT
Voltage on Any Pin with
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outsideofthoselistedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to any absolute maximum rating for extended periods
Respect to Ground(1) ............–2.0 V to VCC + 2.0 V
VCC with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
MIL-STD-883, Test Method 1033 1,000,000
(3)
TDR
Data Retention
MIL-STD-883, Test Method 1008
100
4000
100
(3)
VZAP
ESD Susceptibility MIL-STD-883, Test Method 3015
Latch-up JEDEC Standard 17
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
V
= 1.8 V to 5.5 V, unless otherwise specified.
CC
Symbol
ICC
Parameter
Test Conditions
fSCL = 100 kHz
Min
Typ
Max
Units
mA
mA
µA
Power Supply Current (Read)
Power Supply Current (Write)
Standby Current (VCC = 5.0 V)
Input Leakage Current
1
3
1
1
1
ICC
fSCL = 100 kHz
(5)
ISB
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
ILI
ILO
µA
Output Leakage Current
Input Low Voltage
µA
VIL
–1
VCC x 0.3
VCC + 1.0
0.4
V
V
V
V
VIH
Input High Voltage
VCC x 0.7
VOL1
VOL2
Output Low Voltage (VCC = 3.0 V)
Output Low Voltage (VCC = 1.8 V)
IOL = 3 mA
IOL = 1.5 mA
0.5
CAPACITANCE T = 25°C, f = 400 kHz, V
= 5 V
CC
A
Symbol
Test
Conditions
VI/O = 0 V
VIN = 0 V
Min
Typ
Max
8
Units
pF
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
(3)
CIN
6
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to V + 1.0 V.
CC
(5) Maximum standby current (I ) = 10µA for the Extended Automotive temperature range.
SB
Doc. No. 1054, Rev. G
2
CAT24FC16
A.C. CHARACTERISTICS
V
= 1.8 V to 5.5 V, unless otherwise specified.
CC
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 5.5 V
MinMax
100
2.5 V - 5.5 V
Min Max
itsUn
400
FSCL
TI(1)
Clock Frequency
kHz
ns
Noise Suppression Time
100
100
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
0.9
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.3
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
0.6
1.3
0.6
0.6
µs
µs
µs
µs
4.7
4
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
tHD:DAT
tSU:DAT
Data In Hold Time
0
250
1
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
Parameter
MinTyp
Max
Max
its Un
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
Write Cycle Limits
Symbol
Parameter
MinTyp
its Un
tWR
Write Cycle Time
5
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc No. 1054, Rev. G
3
CAT24FC16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
TheCAT24FC16supportstheI2CBusdatatransmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditionsforbusaccess. TheCAT24FC16operatesas
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
SCL: Serial Clock
TheCAT24FC16serialclockinputpinisusedtoclockall
data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24FC16 bidirectional serial data/address pin is
usedtotransferdataintoandoutofthedevice. TheSDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
theentirememory. ForCAT24FC16whenthispinistied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
t
t
t
Figure 1. Bus Timing
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1054, Rev. G
4
CAT24FC16
I2C BUS PROTOCOL
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The following defines the features of the I2C bus proto-
col:
After the Master sends a START condition and the slave
address byte, the CAT24FC16 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC16 then performs a Read or a Write operation
depending on the state of the R/W bit.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC16 monitor the
SDA and SCL lines and will not respond until this
condition is met.
The CAT24FC16 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
When the CAT24FC16 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC16 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC16 (see Fig. 5). The next three
significant bits (A10, A9, A8) are the memory array
address bits. The last bit of the slave address specifies
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A10 A9
A8 R/W
Normal Read and Write
DEVICE ADDRESS
Doc No. 1054, Rev. G
5
CAT24FC16
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC16 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC16. After receiving another
acknowledgefromtheSlave,theMasterdevicetransmits
the data byte to be written into the addressed memory
location. The CAT24FC16 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT24FC16 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC16 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC16hascompletedthewriteoperation, anACK
will be returned and the host can then proceed with the
next read or write operation.
Page Write
WRITE PROTECTION
The CAT24FC16 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC16 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
The CAT24FC16 is designed with a hardware protect
pin that enables the user to protect the entire memory.
The hardware protection feature of the CAT24FC16 is
designed into the part to provide added flexibility to the
design engineers. The write protection feature of
CAT24FC16allowstheusertoprotectagainstinadvertent
programming of the memory array. If the WP pin is tied
toVcc,theentirememoryarrayisprotectedandbecomes
read only. The entire memory becomes write protected
regardlessofwhetherthewriteprotectregisterhasbeen
written or not. When WP pin is tied to Vcc, the user
cannot program the write protect register. If the WP pin
is left floating or tied to Vss, the device can be written
into.
If the Master transmits more than 16 bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
Figure 6. Byte Write Timing
S
T
S
A
R
T
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1054, Rev. G
6
CAT24FC16
Sequential Read
Read Operations
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC16 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC16 will continue to output a byte for
each acknowledge sent by the Master. The operation
willterminateoperationwhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
The READ operation for the CAT24FC16 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
TheCAT24FC16’saddresscountercontainstheaddress
of the last byte accessed, incremented by one. In other
words,ifthelastREADorWRITEaccesswastoaddress
N, the READ immediately following would access data
from address N + 1. If N = 2047 for 24FC16, then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24FC16 receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
The data being transmitted from the CAT24FC16 is
outputtedsequentiallywithdatafromaddressNfollowed
by data from address N + 1. The READ operation
address counter increments all of the CAT24FC16
addressbitssothattheentirememoryarraycanberead
during one operation. If more than the 2047 bytes are
read out, the counter will “wrap around” and continue to
clock out data bytes.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24FC16 acknowledge the word
address,theMasterdeviceresendstheSTARTcondition
and the slave address, this time with the R/W bit set to
one. The CAT24FC16 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
DATA
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc No. 1054, Rev. G
7
CAT24FC16
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1054, Rev. G
8
CAT24FC16
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
24FC16
J
I
TE13
REV-F
Optional
Company ID
Temperature Range
I = Industri
E = Extended (-40°C to +125°C)
Tape & Reel
Product
Number
Die Revision
Package
P: PDIP
J: SOIC (JEDEC)
R: MSOP
U: TSSOP
RD4: TDFN
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC), (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
ZD4: TDFN (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 24FC16JI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
Doc No. 1054, Rev. G
9
CAT24FC16
REVISION HISTORY
Date
Revision Comments
11/18/03
A
B
Initial Issue
12/09/03
Changed Industrial Temp to “ I” from “ Blank” in ordering
information
03/10/04
04/02/04
C
D
Corrected TDFN ordering info
Eliminated data sheet designation
Removed reference to a write protect register in “ Write Protection”
D.C. Operating Characteristics
Write Cycle Limits
05/15/04
E
Update Ordering Information
Update Revision History
Update Rev Number
06/07/04
7/27/04
F
Update Write Cycle Limits
G
Update notes on page 2
Doc. No. 1054, Rev. G
10
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Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
DPPs ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #: 1054
Revison:
G
Issue date:
07/27/04
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