CAT24FC256LA-1.8 [CATALYST]
EEPROM, 32KX8, Serial, CMOS, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8;
| 型号： | CAT24FC256LA-1.8 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 32KX8, Serial, CMOS, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24FC256
256K-Bit I2C Serial CMOS EEPROM
FEATURES
I Fast mode I2C bus compatible*
I Industrial and automotive
temperature ranges
I Max clock frequency:
I 5 ms max write cycle time
- 400kHz for VCC = 1.8 V to 5.5 V
- 1MHz for VCC = 2.5 V to 5.5 V
I Write protect feature
– Entire array protected when WP at VIH
I Schmitt trigger filtered inputs for noise suppression
I Low power CMOS technology
I 100,000 program/erase cycles
I 100 year data retention
I 64-byte page write buffer
I 8-pin DIP or 8-pin SOIC(JEDEC) and 8-pin SOIC
I Self-timed write cycle with auto-clear
(EIAJ)
DESCRIPTION
TheCAT24FC256isa256K-bitSerialCMOSEEPROM
internally organized as 32,768 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reducesdevicepowerrequirements.TheCAT24FC256
features a 64-byte page write buffer. The device oper-
ates via the I2C bus serial interface and is available in 8-
pin DIP or 8-pin SOIC packages.
BLOCK DIAGRAM
PIN CONFIGURATION
EXTERNAL LOAD
DIP Package (P, L, GL)
SENSE AMPS
SHIFT REGISTERS
D
1
2
3
4
8
7
6
5
V
A0
A1
OUT
CC
ACK
WP
A2
SCL
SDA
V
V
CC
SS
V
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
START/STOP
SOIC Package (J, W, K, X, GW, GX)
SDA
LOGIC
1
2
3
4
8
7
6
5
V
A0
A1
A2
CC
WP
EEPROM
512X512
XDEC
512
SCL
SDA
V
CONTROL
LOGIC
SS
WP
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
A0, A1, A2 Address Inputs
SDA
SCL
WP
VCC
VSS
NC
Serial Data/Address
HIGH VOLTAGE/
TIMING CONTROL
Serial Clock
Write Protect
SCL
STATE COUNTERS
+1.8V to +5.5V Power Supply
Ground
A0
A1
SLAVE
ADDRESS
COMPARATORS
A2
No Connect
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
1
CAT24FC256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
V
CC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch-up
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
MIL-STD-883, Test Method 1033 100,000
(3)
TDR
MIL-STD-883, Test Method 1008
JEDEC Standard 17
100
100
(3)(4)
ILTH
mA
DC OPERATING CHARACTERISTICS
= 1.8 V to 5.5 V, unless otherwise specified.
V
CC
Symbol Parameter
Test Conditions
Min
Typ
Max
Units
I
Power Supply Current - Read
Power Supply Current - Write
Standby Current
f
= 100kHz
SCL
400
µA
CC1
V
CC
= 5V
I
f
= 400kHz
4
mA
CC2
SCL
V
CC
= 5V
(5)
SB
I
V
V
= GND or V
1
µA
IN
CC
V
CC
= 5V
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
= GND to V
1
1
µA
µA
LI
IN
CC
I
V
= GND to V
OUT CC
LO
V
IL
-0.5
V
x 0.3
V
V
V
V
CC
V
Input High Voltage
V
x 0.7
V
+ 0.5
CC
IH
CC
V
Output Low Voltage (V
= +3.0 V)
= +1.8 V)
I
I
= 3.0 mA
= 1.5 mA
0.4
OL1
OL2
CC
CC
OL
V
Output Low Voltage (V
0.5
OL
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP, A0, A1)
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max
8
Units
pF
(3)
CI/O
(3)
CIN
6
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
2
CAT24FC256
AC CHARACTERISTICS
= 1.8V to 5.5 V, unless otherwise specified. Output load is 1 TTL gate and 100pF.
V
CC
Read & Write Cycle Limits
Symbol Parameter
VCC=1.8V - 5.5V
VCC=2.5V - 5.5V
Min
Max
Min
Max
Units
FSCL
tAA
Clock Frequency
400
1000
kHz
SCL Low to SDA Data Out and
ACK Out
0.05
1.3
0.9
0.05
0.5
0.5
µs
µs
Time the Bus Must be Free Before
a New Transmission Can Start
(2)
tBUF
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
0.6
1.3
0.6
0.25
0.6
µs
µs
µs
tHIGH
Clock High Period
0.4
Start Condition Setup Time (for a
Repeated Start Condition)
tSU:STA
0.6
0.25
µs
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
ms
ns
µs
µs
Data In Setup Time
100
20
100
(2)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.3
0.1
(2)
tF
20
300
100
tSU:STO
tDH
0.6
50
0.25
50
tWR
Write Cycle Time
5
5
tSP
Input Suppresssion (SDA, SCL)
WP Setup Time
50
50
tSU;WP
tHD;WP
0.6
1.3
0.5
0.8
WP Hold Time
(2)(3)
Power-Up Timing
Symbol
Parameter
Min
Typ
Max
Units
ms
tPUR
Power-Up to Read Operation
Power-Up to Write Operation
1
1
tPUW
ms
Note:
(1) AC measurement conditions:
RL (connects to V ): 0.3V to 0.7 V
CC
CC
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
3
CAT24FC256
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
TheCAT24FC256supportstheI2CBusdatatransmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC256 operates
as a Slave device. Both the Master device and Slave
device can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1, A2: Device Address Inputs
PIN DESCRIPTIONS
These pins are hardwired or left connected. When
hardwired,uptoeightCAT24FC256'smaybeaddressed
on a single bus system. When the pins are left
unconnected, the default values are zero.
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
AA
DH
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
4
CAT24FC256
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
as many as eight devices on the same bus. These bits
must compare to their hardwired input pins. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT24FC256 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC256 then performs a Read or Write operation
depending on the state of the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC256 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
The CAT24FC256 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC256 uses the next three bits
as address bits. The address bits A2, A1 and A0 allow
WhentheCAT24FC256beginsaREADmodeittransmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge,theCAT24FC256willcontinuetotransmit
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0 R/W
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
5
CAT24FC256
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
IftheMastertransmitsmorethan64bytesbeforesending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24FC256 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC256. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memorylocation.TheCAT24FC256acknowledgesonce
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24FC256 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24FC256 is still busy with the
write operation, no ACK will be returned. If
CAT24FC256 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
WRITE PROTECTION
The CAT24FC256 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24FC256 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain un-
changed.
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24FC256
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device’s failure to send an acknowledge
after the first byte of data is received.
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
15
8
7
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
=Don't Care Bit
*
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
DATA n
DATA n+63
15
8
7
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
=Don't Care Bit
*
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
6
CAT24FC256
slave address and byte addresses of the location it
wishes to read. After CAT24FC256 acknowledges, the
MasterdevicesendstheSTARTconditionandtheslave
address again, this time with the R/W bit set to one. The
CAT24FC256 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
READ OPERATIONS
The READ operation for the CAT24FC256 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
Sequential Read
The CAT24FC256’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
accessdatafromaddressN+1.IfN=E(whereE=32767),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24FC256
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. AftertheCAT24FC256sendstheinitial8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC256 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24FC256 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1.TheREADoperationaddress
counter increments all of the CAT24FC256 address bits
so that the entire memory array can be read during one
operation. If more than E (where E=32767) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
7
CAT24FC256
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
SLAVE
ADDRESS
A
–A
A –A
DATA
15
8
7
0
SDA LINE
S
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
=Don't Care Bit
*
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
8
CAT24FC256
PACKAGE OUTLINES
8–LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
0.355 (9.02)
0.400 (10.16)
0.120 (3.05)
0.180 (4.57) MAX
0.150 (3.81)
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
—
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
9
CAT24FC256
8-LEAD 150 MIL WIDE SOIC (J, W, GW)
0.1890 (4.80)
0.1968 (5.00)
0.0532 (1.35)
0.0688 (1.75)
0.149 (3.80)
0.1574 (4.00)
0.2284 (5.80)
0.2440 (6.20)
0.050 (1.27) BSC
0.0040 (0.10)
0.0098 (0.25)
0.013 (0.33)
0.020 (0.51)
0.0099 (0.25)
0.0196 (0.50)
X 45˚
0.0075 (0.19)
0.0098 (0.25)
0˚-8˚
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
8-LEAD 250 MIL WIDE SOIC (K, X, GX)
0.205 (5.15)
0.210 (5.35)
0.080 (2.03)
MAX
0.205 (5.20)
0.213 (5.40)
0.303 (7.70)
0.318 (8.10)
0.046 (1.17)
0.054 (1.37)
0.0137 (0.35)
0.0177 (0.45)
0.0267 (0.68)
0.0303 (0.77)
0.008 (0.20)
4˚ REF
0.025 (0.65)
Notes:
1. All linear dimensions are in inches and parenthetically in millimeters.
2. Lead coplanarity is 0.004" (0.102mm) maximum.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
10
CAT24FC256
ORDERING INFORMATION
Prefix
Device #
24FC256
Suffix
CAT
J
-1.8
I
TE13
REV-A
Temperature Range
Optional
Company ID
Product
Number
Tape & Reel
I = Industrial (-40˚C to 85˚C)
A = Automotive (-40˚C to 105˚C)
E = Extended (-40˚C to 125˚C)
Die Revision
Package
Operating Voltage
Blank: 2.5 to 5.5 V
1.8: 1.8 to 5.5 V
P: PDIP
K: SOIC, EIAJ
J: SOIC, JEDEC
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
X: SOIC, EIAJ (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a 24FC256JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1040, Rev. K
11
REVISION HISTORY
Date
Revision Comments
12/09/03
01/21/04
03/13/04
E
F
Changed Max Clock Frequency from 6.0V to 5.5V in all instances
Changed Endurance Maximum to 100,000 cycles.
G
Eliminated data sheet designation
Changed VCC power supply from 1.8V to 6.0V to 1.8V to 5.5V
Updated ICC2 Power supply max in DC Operating Characteristics
Added package mechanical drawings
Eliminated Reel quantity in Ordering Information
05/16/04
H
Update D.C. Operating Characteristics
Update Read & Write Cycle Limits
Update Ordering Information
Update Revision History
Update Rev Number
06/07/04
I
Update Read & Write Cycle Limits
Update notes on page 2
7/28/04
J
08/02/05
K
Update Pin Configuration
Update Ordering Information
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Publication #: 1040
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K
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Issue date:
08/02/05
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