CAT24FC32YA-1.8TE13 [CATALYST]
EEPROM, 4KX8, Serial, CMOS, PDSO8, TSSOP-8;
| 型号： | CAT24FC32YA-1.8TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 4KX8, Serial, CMOS, PDSO8, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
CAT24FC32
32K-Bit Fast Mode I2C Serial CMOS EEPROM
FEATURES
■ Fast mode I2C bus compatible*
■ Random and sequential read modes
■ Max clock frequency:
■ Schmitt trigger and spike suppression at SDA
and SCL inputs
400 kHz for VCC=1.8V to 5.5V
■ Output slope control to eliminate ground
1 MHz for VCC=2.5V to 5.5V
bounce
■ Hardware write protect for entire array
■ Cascadable for up to eight devices
■ 32-Byte page or byte write modes
■ Self-timed write cycle with autoclear
■ 5 ms max write cycle time
■ Zero standby current
■ Commercial, industrial and automotive
temperature ranges
■ 1,000,000 program/erase cycles
■ 100 years data retention
■ 8-pin PDIP, 8-pin SOIC (150 and 200 mil) and
8-pin TSSOP packages
DESCRIPTION
The CAT24FC32 is a 32K-bit Serial CMOS EEPROM
internally organized as 4Kx8 bits. The device is
compatible with Fast-mode I2C bus specification and
operates down to 1.8V with a bit rate up to 400 kbit/s and
1MHz for VCC ≥ 2.5V. Extended addressing capability
allows up to 8 devices to share the same bus. Catalyst's
advanced CMOS technology substantially reduces
device power requirements. The device is optimized for
high performance applications, where low power, low
voltage and high speed operation are required.
CAT24FC32isavailablein8-pinDIP,8-pinSOIC(JEDEC
and EIAJ) and 8-pin TSSOP packages.
PIN CONFIGURATION
BLOCK DIAGRAM
EXTERNAL LOAD
TSSOP Package (U)
DIP Package (P)
SENSE AMPS
SHIFT REGISTERS
D
OUT
1
2
3
4
8
7
6
5
ACK
A
A
A
V
0
1
2
1
2
3
4
8
7
6
5
CC
A
V
CC
WP
0
WP
V
CC
A
1
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SCL
SDA
V
SS
A
SCL
SDA
2
V
SS
V
SS
256
START/STOP
LOGIC
SDA
SOIC Package (J,K)
EEPROM
128 X 256
XDEC 128
CONTROL
LOGIC
WP
1
2
3
4
8
7
6
5
A
A
A
V
CC
WP
0
1
2
SCL
SDA
V
DATA IN STORAGE
SS
HIGH VOLTAGE/
TIMING CONTROL
SCL
STATE COUNTERS
SLAVE
A
0
ADDRESS
COMPARATORS
A1
A2
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1020, Rev. F
1
CAT24FC32
Advance Information
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
SDA
Device Address Inputs
Serial Data/Address
Serial Clock
SCL
WP
Write Protect
VCC
Power Supply
Ground
VSS
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
RECOMMENDED OPERATING CONDITIONS
Temperature Range
Commercial
Industrial
Minimum
0˚C
Maximum
+70˚C
+85˚C
-40˚C
-40˚C
-40˚C
Automotive
+105˚C
+125˚C
Extended
Supply Voltage Range
2.5V to 5.5V
Device
CAT24FC32
CAT24FC32-1.8
1.8V to 5.5V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1020, Rev. F
2
Advance Information
CAT24FC32
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions, unless otherwise specified
Symbol
Parameter
Min.
-10
Typ.
Max.
10
Units
µA
Test Conditions
(4)
I
I
I
Input Leakage Current
V
V
= GND to V
= GND to V
LI
IN
CC
CC
(4)
Output Leakage Current
-10
10
µA
LO
CC1
IN
Power Supply Current
(Operating Write)
3
mA
f
= 400kHz
= 5.5V
SCL
V
CC
I
Power Supply Current
(Operating Read)
400
0
µA
µA
f
= 400kHz
= 5.5V
CC2
SCL
V
CC
CC
(1)
SB
I
Standby Current
V
V
= 5.5V
= GND or V
IN
CC
(2)
(2)
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3V
V
V
V
IL
CC
0.7V
V + 0.5
CC
IH
CC
0.4
2.5V ≤ V
≤ 5.5V
CC
OL1
I
= 3.0 mA
OL
V
Output Low Voltage
0.2V
V
1.8V ≤ V
< 2.5V
CC
OL2
CC
I
= 3 mA
OL
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
Units
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
8
6
pF
pF
(3)
CIN
Note:
(1) Standby current, I < 900 nA; A0, A1, A2, WP connected to GND; SCL, SDA = GND or VCC.
SB
(2)
V min and V max are reference values only and are not tested.
IL IH
(3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(4) I/O pins, SDA and SCL do not obstruct the bus lines if V is switched off.
CC
Doc. No. 1020, Rev. F
3
CAT24FC32
Advance Information
A.C. CHARACTERISTICS
Over recommended operating conditions, unless otherwise specified (Note 1).
Read & Write Cycle Limits
Symbol
Parameter
VCC = 1.8V - 5.5V
VCC = 2.5V - 5.5V
Units
Min.
Max.
400
50
Min.
Max.
1,000
50
fSCL
tSP
Clock Frequency
kHz
ns
Input Filter Spike
Suppression (SDA, SCL)
tLOW
tHIGH
Clock Low Period
1.3
0.6
20
0.6
0.4
20
µs
µs
ns
ns
µs
µs
Clock High Period
(2)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
300
300
300
100
(2)
tF
20
20
tHD:STA
0.6
0.6
0.25
0.25
tSU:STA
Start Condition Setup Time
(for a Repeated Start)
tHD:DAT
tSU:DAT
tSU:STO
tSU:WP
tHD:WP
tAA
Data Input Hold Time
Data In Setup Time
Stop Condition Setup Time
WP Setup Time
0
0
50
0.25
0
ns
ns
µs
µs
µs
ns
ns
µs
100
0.6
0
WP Hold Time
2.5
1
SCL Low to Data Out Valid
Data Out Hold Time
900
550
tDH
50
50
(2)
tBUF
Time the Bus must be Free Before
a New Transmission Can Start
1.3
0.5
(2)
tOF
Output Fall Time from VIH min to
VIL max
20
250
5
20
100
5
ns
(3)
tWC
Write Cycle Time (Byte or Page)
ms
(2)(4)
Power-Up Timing
Symbol
Parameter
Max.
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
1
ms
ms
Note:
(1) Test Conditions according to "AC Test Conditions" Table.
(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
(4) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1020, Rev. F
4
Advance Information
CAT24FC32
AC TEST CONDITIONS
Input pulse voltages
Input rise and fall times
Input reference voltages
Output reference voltages
Output load
0.2VCC to 0.8VCC
≤ 50 ns
0.3VCC, 0.7VCC
0.5VCC
Current source: IOL = 3mA;
CL: 400pF for fSCl max = 400kHz / 100pF for fSCL max = 1 MHz
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
AA
DH
SDA OUT
Figure 2. WP Timing
2nd Byte Address
Data
1
8
9
1
8
SCL
SDA
A
7
A
0
D
7
D
0
t
SU:WP
WP
t
HD:WP
Figure 3. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc. No. 1020, Rev. F
5
CAT24FC32
Advance Information
PIN DESCRIPTION
SCL: Serial Clock
WP: Write Protect
This input controls the device write protect feature. WP
pinconnectedtoVSS allowswriteoperationstotheentire
memory. When this pin is connected to Vcc, the entire
memoryiswriteprotected. Whenleftfloating,aninternal
pull-down resistor on this input will keep the memory
unprotected. Read operations are not affected.
The serial clock input clocks all data transferred into or
outofthedevice. TheSCLlinerequiresapull-upresistor
if it is driven by an open drain output.
SDA: Serial Data/Address
A0, A1, A2: Device Address Inputs
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs. A pull-up resistor
must be connected from SDA line to Vcc. The value of
the pull-up resistor, Rp, can be calculated based on
minimumandmaximumvaluesfromFigure4andFigure
5. (see Note).
Theseinputsareusedforextendedaddressingcapability.
The A0, A1, A2 pins can be hardwired to VCC or VSS, or
left unconnected. When hardwired, up to eight
CAT24FC32smaybeaddressedonasinglebussystem.
When the pins are left unconnected, the default values
are zero. The levels on these inputs are compared with
corresponding bits, A2, A1, A0, from the slave address
byte.
Minimum R as a Function of Supply Voltage
P
Minimum R Value versus Bus Capacitance
P
2
(Fast Mode I C Bus / tr max = 300ns)
(IOL = 3mA @ VOLmax)
8.00
2.5
2
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
1.5
1
0.5
0
1.6
2
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2 5.6
6
50
100 150 200 250 300
350 400
V
(V)
Cbus (pF)
CC
Figure 4
Figure 5
Note: According to the Fast Mode I2C bus specification, for bus capacitance up to 200pF, the pull up device
can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source
(Imax=3mA) or a switched resistor circuit.
Doc. No. 1020, Rev. F
6
Advance Information
CAT24FC32
FUNCTIONAL DESCRIPTION
SDA when SCL is HIGH. The CAT24FC32 monitors the
SDA and SCL lines and will not respond until this
condition is met.
TheCAT24FC32supportstheI2CBusdatatransmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditionsforbusaccess. TheCAT24FC32operatesas
aSlavedevice.BoththeMasterdeviceandSlavedevice
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT24FC32 for
a read or write operation (Figure 7). The four most
significant bits of the 8-bit slave address are fixed as
binary 1010. The CAT24FC32 uses the next three bits
as address bits. The address bits A2, A1 and A0 are
used to select which device is accessed from maximum
eightdevicesonthesamebus. Thesebitsmustcompare
to their hardwired input pins. The last bit of the slave
address specifies whether a read or write operation is to
beperformed. Whenthisbitissetto“1”,areadoperation
is initiated, and when set to “0”, a write operation is
selected.
I2C Bus Protocol
2
The features of the I C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpretedasaSTARTorSTOPcondition(Figure
6).
Following the START condition and the slave address
byte, the CAT24FC32 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matchesthetransmittedslaveaddress. TheCAT24FC32
then performs a read or write operation depending on
the state of the R/W bit.
START Condition
The START condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 6. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 7. Slave Address Bits
1
0
1
0
A2
A1
A0 R/W
Doc. No. 1020, Rev. F
7
CAT24FC32
Acknowledge
Advance Information
WRITE OPERATIONS
Byte Write
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data. The SDA line remains stable LOW during the
HIGH period of the acknowledge related clock pulse
(Figure 8).
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC32. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24FC32 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
The CAT24FC32 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte. The CAT24FC32 does not generate
acknowledge if an internal write cycle is in progress.
WhentheCAT24FC32beginsaREADmodeittransmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24FC32 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition. The master must then issue a stop condition
to return the CAT24FC32 to the standby power mode
and place the device in a known state.
Page Write
TheCAT24FC32writesupto32bytesofdata,inasingle
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has
Figure 8. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 9. Byte Write Timing
S
T
A
R
T
S
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
O
P
A
—A
A —A
DATA
15
X
8
7
0
SDA LINE
S
P
X X X
A
C
K
A
C
K
A
C
K
A
C
K
X = Don't care bit
Doc. No. 1020, Rev. F
8
Advance Information
CAT24FC32
WRITE PROTECTION
been transmitted, CAT24FC32 will respond with an
acknowledge,andinternallyincrementthefiveloworder
address bits by one. The high order bits remain
unchanged.
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is connected to V , the entire memory
CC
array is protected and becomes read only. The
CAT24FC32 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received. The
WP input is sampled in the end of acknowledge pulse
after second address byte, accordingly with setup and
hold times relative to negative clock edge (Figure 2).
If the Master transmits more than 32 bytes before
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24FC32 in a single write cycle.
Acknowledge Polling
READ OPERATIONS
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation,
CAT24FC32initiatestheinternalwritecycle.ACKpolling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation. If CAT24FC32 is still busy with the write
operation, no ACK will be returned. If CAT24FC32 has
completed the write operation, an ACK will be returned
andthehostcanthenproceedwiththenextreadorwrite
operation.
The READ operation for the CAT24FC32 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
TheCAT24FC32’saddresscountercontainstheaddress
of the last byte accessed, incremented by one. In other
words,ifthelastREADorWRITEaccesswastoaddress
Figure 10. Page Write Timing
S
T
S
T
O
P
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
A
—A
A —A
DATA
DATA n
DATA n+31
15
8
7
0
SDA LINE
S
P
X X X X
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
X=Don't care bit
Figure 11. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 1020, Rev. F
9
CAT24FC32
Advance Information
N, the READ immediately following would access data
from address N+1. If N=E (where E=4095), then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24FC32 receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8 bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC32 sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC32 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After CAT24FC32 acknowledges, the
Master device sends the START condition and the
slave address again, this time with the R/W bit set to
one. The CAT24FC32 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
ThedatabeingtransmittedfromCAT24FC32isoutputted
sequentially with data from address N followed by data
fromaddressN+1.TheREADoperationaddresscounter
increments all of the CAT24FC32 address bits so that
theentirememoryarraycanbereadduringoneoperation.
After the last memory address is read out, the counter
will ‘wrap around’ and continue to clock out data bytes.
Figure 12. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
—A A —A
0
SLAVE
ADDRESS
A
DATA
15
8
7
SDA LINE
S
S
P
X X X X
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
X = Don't care bit
Figure 13. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1020, Rev. F
10
Advance Information
CAT24FC32
ORDERING INFORMATION
Prefix
Device #
24FC32
Suffix
CAT
-1.8
TE13
K
I
Temperature Range
Optional
Company ID
Tape & Reel
TE13: 2000/Reel
Product
Number
to
to
A =
to
to
*
Package
Operating Voltage
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
P: PDIP
K: SOIC (EIAJ)
J: SOIC (JEDEC)
U: TSSOP
Notes:
(1) The device used in the above example is a CAT24FC32KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
Doc. No. 1020, Rev. F
11
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
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Catalyst Semiconductor, Inc.
Corporate Headquarters
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Publication #: 1020
Revison:
Issue date:
Type:
F
5/22/03
Advance
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