CAT24FC65LI [CATALYST]
CAT24FC65LI;
| 型号： | CAT24FC65LI |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | CAT24FC65LI |
| 文件： | 总10页 (文件大小：627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24FC65, CAT24FC66
64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection
FEATURES
I Fast mode I2C bus compatible*
I 5 ms max write cycle time
I Max clock frequency:
I Write protect feature
- 400KHz for VCC=2.5V to 5.5V
– Bottom 1/4 array protected when WP at VIH
(CAT24FC65)
– Top 1/4 array protected when WP at VIH
(CAT24FC66)
I Schmitt trigger filtered inputs for
noise suppression
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
I 64-byte page write buffer
I Self-timed write cycle with auto-clear
I Industrial and automotive temperature ranges
I 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
TheCAT24FC65/66isa64k-bitSerialCMOSEEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements.
The CAT24FC65/66 features a 64-byte page write
buffer. The device operates via the I2C bus serial
interface and is available in 8-pin DIP, SOIC, TSSOP
and TDFN packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L, GL)
TDFN Package (RD2, ZD2)
EXTERNAL LOAD
1
2
3
4
8
7
6
5
8
7
6
5
V
CC
A0
A1
1
2
3
4
V
SENSE AMPS
SHIFT REGISTERS
A0
A1
CC
D
OUT
WP
WP
ACK
A2
A2
SCL
SDA
SCL
SDA
V
V
CC
SS
V
VSS
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
(Top View)
SOIC Package
(J, W, K, X, GW, GX)
512
TSSOP Package (U, Y, GY)
START/STOP
SDA
LOGIC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
A0
A1
A2
A0
A1
A2
CC
CC
WP
WP
SCL
SDA
EEPROM
128X512
SCL
SDA
XDEC
128
V
V
SS
SS
CONTROL
LOGIC
WP
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Address Inputs
DATA IN STORAGE
SDA
SCL
WP
VCC
VSS
NC
Serial Data/Address
HIGH VOLTAGE/
TIMING CONTROL
Serial Clock
Write Protect
SCL
STATE COUNTERS
+2.5V to +5.5V Power Supply
Ground
A0
A1
SLAVE
ADDRESS
COMPARATORS
A2
No Connect
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1047, Rev. H
1
CAT24FC65/66
Package Power Dissipation
ABSOLUTE MAXIMUM RATINGS*
Capability (Ta = 25°C)................................... 1.0W
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
*COMMENT
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outsideofthoselistedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
V
CC with Respect to Ground ............... –2.0V to +7.0V
RELIABILITY CHARACTERISTICS (3)
Symbol
NEND
TDR
Parameter
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
Endurance
Data Retention
ESD Susceptibility
Latch-up
VZAP
4000
Volts
(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +2.5V to +5.5V, unless otherwise specified.
V
CC
Symbol Parameter
Test Conditions
Min
Typ
Max
Units
I
Power Supply Current - Read
Power Supply Current - Write
Standby Current
f
= 400 KHz
SCL
400
µA
CC1
V
CC
=5V
I
f
= 400KHz
3
mA
CC2
SCL
V
=5V
CC
(5)
SB
I
V
V
= GND or V
1
µA
IN
CC
V
CC
=5V
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
= GND to V
1
1
µA
µA
LI
IN
CC
I
V
= GND to V
LO
OUT CC
V
IL
IH
-0.5
V
x 0.3
V
V
V
CC
V
Input High Voltage
V
x 0.7
V
+ 0.5
CC
CC
V
Output Low Voltage (V
= +3.0V)
I = 3.0 mA
OL
0.4
OL1
CC
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Input/Output Capacitance (SDA)
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max
8
Units
pF
(3)
CI/O
(3)
CIN
Input Capacitance (SCL, WP, A0, A1)
WP Input Impedance
6
pF
ZWPL
ZWPH
VIN ≤ 0.5V
5
70
kΩ
WP Input Impedance
VIN>0.7VxVCC
500
kΩ
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby current (I ) = 10 µA max at extended temperature range.
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1047, Rev. H
2
CAT24FC65/66
A.C. CHARACTERISTICS
= +2.5V to +5.5V, unless otherwise specified
V
CC
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
VCC=2.5V - 5.5V
Min
Max
400
900
Units
kHz
ns
FSCL
tAA
Clock Frequency
SCL Low to SDA Data Out and ACK Out
50
Time the Bus Must be Free Before a New Transmission
Can Start
(2)
tBUF
1300
ns
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
600
1300
600
600
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
tHIGH
Clock High Period
tSU:STA
tHD:DAT
tSU:DAT
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
100
(2)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
300
300
(2)
tF
tSU:STO
tDH
600
50
tWR
Write Cycle Time
5
tSP
Input Suppresssion (SDA, SCL)
WP Setup Time
50
tSU;WP
tHD;WP
600
WP Hold Time
1300
(2)(3)
Power-Up Timing
Symbol Parameter
Min
Typ
Max
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
1
ms
ms
Note:
(1) AC measurement conditions:
RL (connects to V ): 0.3V to 0.7 V
CC
CC
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1047, Rev. H
3
CAT24FC65/66
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
The CAT24FC65/66 supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24FC65/66
operates as a Slave device. Both the Master device and
Slavedevicecanoperateaseithertransmitterorreceiver,
but the Master device controls which mode is activated.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
bottom/top (CAT24FC65/CAT24FC66)1/4 of memory
is write protected. When left floating, memory is
unprotected.
PIN DESCRIPTIONS
A0, A1, A2: Device Address Inputs
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC65/66's may be
addressed on a single bus system. When the pins are
left unconnected, the default values are zero.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
AA
DH
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1047, Rev. H
4
CAT24FC65/66
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
allow as many as eight devices on the same bus. These
bitsmustcomparetotheirhardwiredinputpins. Thelast
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT24FC65/66 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC65/66thenperformsaReadorWriteoperation
depending on the state of the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC65/66 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
The CAT24FC65/66 responds with an acknowledge
afterreceivingaSTARTconditionanditsslaveaddress.
If the device has been selected along with a write
operation,itrespondswithanacknowledgeafterreceiving
each 8-bit byte.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC65/66 uses the next three
bits as address bits. The address bits A2, A1 and A0
When the CAT24FC65/66 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24FC65/66 will continue to
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0 R/W
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1047, Rev. H
5
CAT24FC65/66
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
IftheMastertransmitsmorethan64bytesbeforesending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24FC65/66 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC65/66. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24FC65/66 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24FC65/66 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24FC65/66 is still busy with the
write operation, no ACK will be returned. If
CAT24FC65/66 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
WRITE PROTECTION
The CAT24FC65/66 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24FC65/66 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain un-
changed.
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24FC65/66
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device’s failure to send an acknowledge
after the first byte of data is received.
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
15
8
7
SDA LINE
S
P
**
*
A
C
K
A
C
K
A
C
K
A
C
K
=Don't Care Bit
*
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
DATA n
DATA n+63
15
8
7
SDA LINE
S
P
*
*
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
=Don't Care Bit
*
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1047, Rev. H
6
CAT24FC65/66
slave address and byte addresses of the location it
wishes to read. After CAT24FC65/66 acknowledges,
the Master device sends the START condition and the
slaveaddressagain,thistimewiththeR/Wbitsettoone.
TheCAT24FC65/66thenrespondswithitsacknowledge
and sends the 8-bit byte requested. The master device
doesnotsendanacknowledgebutwillgenerateaSTOP
condition.
READ OPERATIONS
The READ operation for the CAT24FC65/66 is initiated
in the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
Sequential Read
The CAT24FC65/66’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
accessdatafromaddressN+1. IfN=E(whereE=8,191),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24FC65/66
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC65/66 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. TheCAT24FC65/66willcontinuetooutputan8-bit
byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24FC65/66 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1.TheREADoperationaddress
counter increments all of the CAT24FC65/66 address
bits so that the entire memory array can be read during
oneoperation. IfmorethanE(whereE=8,191)bytesare
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1047, Rev. H
7
CAT24FC65/66
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
SLAVE
ADDRESS
A
DATA
15
8
7
SDA LINE
S
S
P
**
*
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
=Don't Care Bit
*
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1047, Rev. H
8
CAT24FC65/66
ORDERING INFORMATION
Prefix
Device #
24FC66
Suffix
CAT
J
I
-1.8
TE13
REV-D
Temperature Range
Optional
Company ID
Product
Number
24FC65
Tape & Reel
I = Industrial (-40˚C to 85˚C)
A = Automotive (-40˚C to 105˚C)
E = Extended (-40˚C to 125˚C)
24FC66
Die Revision
Package
Operating Voltage
Blank: 2.5 to 5.5V
P: PDIP
K: SOIC, EIAJ
J: SOIC, JEDEC
U: TSSOP
RD2: TDFN
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
X: SOIC, EIAJ (Lead-free, Halogen-free)
ZD2: TDFN (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a 24FC66JI-TE13 REV-D (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1047, Rev. H
9
REVISION HISTORY
Date
Revision Comments
07/28/03
02/26/04
04/02/04
05/16/04
A
B
C
D
Initial Issue
Added 8-pin TSSOP package (updated in all areas)
Eliminated data sheet designation
Update D.C. Operating Characteristics
Update Read & Write Cycle Limits
Update Ordering Information
Update Revision History
Update Rev Number
06/07/04
08/25/04
03/24/05
E
F
Update Read & Write Cycle Limits
Update Ordering Information and notes
G
Update Features
Update Description
Update Pin Functions
Update Reliability Characteristics
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update Ordering Information
08/03/05
H
Update Pin Configuration
Update Ordering Information
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Publication #: 1047
Fax: 408.542.1200
Revison:
H
www.caalyst-semiconductor.com
Issue date:
08/03/05
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