CAT24WC01J-1.8TE13F [CATALYST]

1K/2K/4K/8K/16K-Bit Serial E2PROM; 1K / 2K / 4K / 8K / 16K位串行E2PROM
CAT24WC01J-1.8TE13F
型号: CAT24WC01J-1.8TE13F
厂家: CATALYST SEMICONDUCTOR    CATALYST SEMICONDUCTOR
描述:

1K/2K/4K/8K/16K-Bit Serial E2PROM
1K / 2K / 4K / 8K / 16K位串行E2PROM

可编程只读存储器
文件: 总9页 (文件大小:48K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CAT24WC01/02/04/08/16  
1K/2K/4K/8K/16K-Bit Serial E2PROM  
FEATURES  
Self-Timed Write Cycle with Auto-Clear  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
400 KHZ I2C Bus Compatible*  
1.8 to 6.0Volt Operation  
Low Power CMOS Technology  
8-pin DIP, 8-pin SOIC or 8 pin TSSOP  
Write Protect Feature  
Commercial, Industrial and Automotive  
— Entire Array Protected When WP at VIH  
Temperature Ranges  
Page Write Buffer  
DESCRIPTION  
08/16 feature a 16-byte page write buffer. The device  
operates via the I2C bus serial interface, has a special  
write protection feature, and is available in 8-pin DIP, 8-  
pin SOIC or 8-pin TSSOP.  
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-  
bit Serial CMOS E2PROM internally organized as 128/  
256/512/1024/2048 words of 8 bits each. Catalyst’s  
advanced CMOS technology substantially reduces de-  
vice power requirements. The the CAT24WC01/02/04/  
PIN CONFIGURATION  
BLOCK DIAGRAM  
SOIC Package (J)  
DIP Package (P)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
0
1
2
CC  
0
1
2
V
CC  
WP  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
WP  
ACK  
SCL  
SDA  
SCL  
SDA  
V
V
V
SS  
CC  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
V
SS  
5020 FHD F01  
TSSOP Package (U)  
(* Available for 24WC01 and 24WC02 only)  
START/STOP  
SDA  
WP  
LOGIC  
1
2
3
4
8
7
6
5
A
A
A
0
1
2
V
CC  
WP  
E2PROM  
XDEC  
SCL  
SDA  
V
CONTROL  
LOGIC  
SS  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
A0, A1, A2  
SDA  
Device Address Inputs  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
SCL  
SCL  
STATE COUNTERS  
WP  
Write Protect  
SLAVE  
ADDRESS  
COMPARATORS  
A
0
A1  
A2  
VCC  
+1.8V to +6.0V Power Supply  
Ground  
VSS  
24WCXX F03  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© 1999 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25051-00 3/98  
S-1  
1
CAT24WC01/02/04/08/16  
ABSOLUTE MAXIMUM RATINGS*  
*COMMENT  
Temperature Under Bias ................. –55°C to +125°C  
Storage Temperature....................... –65°C to +150°C  
Stresses above those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device.  
These are stress ratings only, and functional operation of  
the device at these or any other conditions outside of those  
listed in the operational sections of this specification is not  
implied. Exposure to any absolute maximum rating for  
extended periods may affect device performance and  
reliability.  
Voltage on Any Pin with  
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V  
VCC with Respect to Ground ............... –2.0V to +7.0V  
Package Power Dissipation  
Capability (Ta = 25°C) .................................. 1.0W  
Lead Soldering Temperature (10 secs) ............ 300°C  
Output Short Circuit Current(2) ........................ 100mA  
RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Min.  
1,000,000  
100  
Max.  
Units  
Cycles/Byte  
Years  
Reference Test Method  
MIL-STD-883, Test Method 1033  
MIL-STD-883, Test Method 1008  
MIL-STD-883, Test Method 3015  
JEDEC Standard 17  
(3)  
NEND  
(3)  
TDR  
Data Retention  
ESD Susceptibility  
Latch-up  
(3)  
VZAP  
2000  
Volts  
(3)(4)  
ILTH  
100  
mA  
D.C. OPERATING CHARACTERISTICS  
V
= +1.8V to +6.0V, unless otherwise specified.  
CC  
Limits  
Typ.  
Symbol  
Parameter  
Min.  
Max.  
Units  
mA  
µA  
µA  
µA  
V
Test Conditions  
fSCL = 100 KHz  
ICC  
Power Supply Current  
3
(5)  
ISB  
Standby Current (VCC = 5.0V)  
Input Leakage Current  
0
10  
VIN = GND or VCC  
VIN = GND to VCC  
VOUT = GND to VCC  
ILI  
ILO  
Output Leakage Current  
Input Low Voltage  
10  
VIL  
–1  
VCC x 0.3  
VCC + 0.5  
0.4  
VIH  
Input High Voltage  
VCC x 0.7  
V
VOL1  
VOL2  
Output Low Voltage (VCC = 3.0V)  
Output Low Voltage (VCC = 1.8V)  
V
IOL = 3 mA  
0.5  
V
IOL = 1.5 mA  
CAPACITANCE T = 25°C, f = 1.0 MHz, V  
= 5V  
CC  
A
Symbol  
Test  
Input/Output Capacitance (SDA)  
Input Capacitance (A0, A1, A2, SCL, WP)  
Max.  
Units  
Conditions  
VI/O = 0V  
VIN = 0V  
(3)  
CI/O  
8
6
pF  
pF  
(3)  
CIN  
Note:  
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.  
CC  
CC  
(2) Output shorted for no more than one second. No more than one output shorted at a time.  
(3) This parameter is tested initially and after a design or process change that affects the parameter.  
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.  
CC  
(5) Standby Current (I ) = 0µA (<900nA).  
SB  
Doc. No. 25051-00 3/98 S-1  
2
CAT24WC01/02/04/08/16  
A.C. CHARACTERISTICS  
V
CC  
= +1.8V to +6.0V, unless otherwise specified.  
Read & Write Cycle Limits  
Symbol  
Parameter  
1.8V, 2.5V  
4.5V-5.5V  
Min.  
Max.  
Min.  
Max.  
Units  
kHz  
ns  
FSCL  
TI(1)  
Clock Frequency  
100  
200  
400  
200  
Noise Suppression Time  
Constant at SCL, SDA Inputs  
tAA  
SCL Low to SDA Data Out  
and ACK Out  
3.5  
1
µs  
µs  
(1)  
tBUF  
Time the Bus Must be Free Before  
a New Transmission Can Start  
4.7  
1.2  
tHD:STA  
tLOW  
Start Condition Hold Time  
Clock Low Period  
4
0.6  
1.2  
0.6  
0.6  
µs  
µs  
µs  
µs  
4.7  
4
tHIGH  
Clock High Period  
tSU:STA  
Start Condition Setup Time  
4.7  
(for a Repeated Start Condition)  
tHD:DAT  
tSU:DAT  
Data In Hold Time  
0
0
ns  
ns  
µs  
ns  
µs  
ns  
Data In Setup Time  
50  
50  
(1)  
tR  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
Stop Condition Setup Time  
Data Out Hold Time  
1
0.3  
(1)  
tF  
300  
300  
tSU:STO  
tDH  
4
0.6  
100  
100  
(1)(2)  
Power-Up Timing  
Symbol  
tPUR  
Parameter  
Max.  
Units  
Power-up to Read Operation  
Power-up to Write Operation  
1
1
ms  
ms  
tPUW  
Write Cycle Limits  
Symbol  
Parameter  
Min.  
Typ.  
Max  
Units  
tWR  
Write Cycle Time  
10  
ms  
interface circuits are disabled, SDA is allowed to remain  
high, and the device does not respond to its slave  
address.  
The write cycle time is the time from a valid stop  
condition of a write sequence to the end of the internal  
program/erase cycle. During the write cycle, the bus  
Note:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
(2) t  
and t  
are the delays required from the time V is stable until the specified operation can be initiated.  
PUR  
PUW  
CC  
Doc. No. 25051-00 3/98 S-1  
3
CAT24WC01/02/04/08/16  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The CAT24WC01/02/04/08/16 supports the I2C Bus  
data transmission protocol. This Inter-Integrated Circuit  
Bus protocol defines any device that sends data to the  
bus to be a transmitter and any device receiving data to  
be a receiver. Data transfer is controlled by the Master  
device which generates the serial clock and all START  
andSTOPconditionsforbusaccess.TheCAT24WC01/  
02/04/08/16 operates as a Slave device. Both the Mas-  
ter and Slave devices can operate as either transmitter  
or receiver, but the Master device controls which mode  
is activated. A maximum of 8 devices (24WC01 and  
24WC02), 4 devices (24WC04), 2 devices (24WC08)  
and 1 device (24WC16) may be connected to the bus as  
determinedbythedeviceaddressinputsA0,A1,andA2.  
SCL: Serial Clock  
The CAT24WC01/02/04/08/16 serial clock input pin is  
used to clock all data transfers into or out of the device.  
This is an input pin.  
SDA: Serial Data/Address  
The CAT24WC01/02/04/08/16 bidirectional serial data/  
address pin is used to transfer data into and out of the  
device. The SDA pin is an open drain output and can be  
wire-ORed with other open drain or open collector  
outputs.  
A0, A1, A2: Device Address Inputs  
These inputs set device address when cascading mul-  
tiple devices. When these pins are left floating the  
default values are zeros (except for the 24WC01).  
A maximum of eight devices can be cascaded when  
Figure 1. Bus Timing  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
SU:STA  
HD:DAT  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
BUF  
SDA IN  
t
t
AA  
DH  
SDA OUT  
5020 FHD F03  
Figure 2. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
5020 FHD F04  
Figure 3. Start/Stop Timing  
SDA  
SCL  
5020 FHD F05  
START BIT  
STOP BIT  
Doc. No. 25051-00 3/98 S-1  
4
CAT24WC01/02/04/08/16  
using either 24WC01 or 24WC02 device. All three  
address pins are used for these densities. If only one  
24WC02 is addressed on the bus, all three address pins  
(A0, A1and A2) can be left floating or connected to VSS.  
If only one 24WC01 is addressed on the bus, all three  
address pins (A0, A1and A2) must be connected to VSS.  
(2) During a data transfer, the data line must remain  
stable whenever the clock line is high. Any changes  
in the data line while the clock line is high will be  
interpreted as a START or STOP condition.  
START Condition  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
SDAwhenSCLisHIGH. TheCAT24WC01/02/04/08/16  
monitortheSDAandSCLlinesandwillnotresponduntil  
this condition is met.  
A total of four devices can be addressed on a single bus  
when using 24WC04 device. Only A1 and A2 address  
pins are used with this device. The A0 address pin is a  
no connect pin and can be tied to VSS or left floating. If  
only one 24WC04 is being addressed on the bus, the  
address pins (A1 and A2) can be left floating or con-  
nected to VSS.  
STOP Condition  
A LOW to HIGH transition of SDA when SCL is HIGH  
determinestheSTOPcondition.Alloperationsmustend  
with a STOP condition.  
Onlytwodevicescanbecascadedwhenusing24WC08.  
TheonlyaddresspinusedwiththisdeviceisA2. TheA0  
andA1addresspinsarenoconnectpinsandcanbetied  
to VSS or left floating. If only one 24WC08 is being  
addressed on the bus, the address pin (A2) can be left  
floating or connected to VSS.  
DEVICE ADDRESSING  
The bus Master begins a transmission by sending a  
START condition. The Master then sends the address  
of the particular slave device it is requesting. The four  
most significant bits of the 8-bit slave address are fixed  
as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).  
Thenextthreesignificantbits(A2,A1,A0)arethedevice  
addressbitsanddefinewhichdeviceorwhichpartofthe  
devicetheMasterisaccessing. UptoeightCAT24WC01/  
02, four CAT24WC04, two CAT24WC08, and one  
CAT24WC16 may be individually addressed by the  
system. The last bit of the slave address specifies  
whether a Read or Write operation is to be performed.  
When this bit is set to 1, a Read operation is selected,  
and when set to 0, a Write operation is selected.  
The 24WC16 is a stand alone device. In this case, all  
address pins (A0, A1and A2) are no connect pins and  
can be tied to VSS or left floating.  
WP: Write Protect  
If the WP pin is tied to VCC the entire memory array  
becomes Write Protected (READ only). When the WP  
pin is tied to VSS or left floating normal read/write opera-  
tions are allowed to the device.  
I2C BUS PROTOCOL  
The following defines the features of the I2C bus proto-  
col:  
After the Master sends a START condition and the slave  
address byte, the CAT24WC01/02/04/08/16 monitors  
the bus and responds with an acknowledge (on the SDA  
(1) Data transfer may be initiated only when the bus is  
not busy.  
Figure 4. Acknowledge Timing  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
5020 FHD F06  
Doc. No. 25051-00 3/98 S-1  
5
CAT24WC01/02/04/08/16  
Figure 5. Slave Address Bits  
24WC01/02  
1
0
1
0
A2  
A1  
A0 R/W  
24WC04  
24WC08  
24WC16  
1
1
1
0
0
0
1
1
1
0
0
0
A2  
A2  
A1  
a9  
a8 R/W  
a8 R/W  
a8 R/W  
a10 a9  
*
A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.  
** a8, a9 and a10 correspond to the address of the memory array address word.  
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).  
line) when its address matches the transmitted slave  
WRITE OPERATIONS  
address. The CAT24WC01/02/04/08/16 then performs  
a Read or Write operation depending on the state of the  
R/W bit.  
Byte Write  
In the Byte Write mode, the Master device sends the  
START condition and the slave address information  
(with the R/W bit set to zero) to the Slave device. After  
the Slave generates an acknowledge, the Master sends  
the byte address that is to be written into the address  
pointer of the CAT24WC01/02/04/08/16. After receiving  
another acknowledge from the Slave, the Master device  
transmits the data byte to be written into the addressed  
memory location. The CAT24WC01/02/04/08/16 ac-  
knowledge once more and the Master generates the  
STOP condition, at which time the device begins its  
internalprogrammingcycletononvolatilememory.While  
this internal cycle is in progress, the device will not  
respond to any request from the Master device.  
Acknowledge  
Afterasuccessfuldatatransfer, eachreceivingdeviceis  
requiredtogenerateanacknowledge.TheAcknowledg-  
ing device pulls down the SDA line during the ninth clock  
cycle, signaling that it received the 8 bits of data.  
The CAT24WC01/02/04/08/16 responds with an ac-  
knowledge after receiving a START condition and its  
slave address. If the device has been selected along  
with a write operation, it responds with an acknowledge  
after receiving each 8-bit byte.  
When the CAT24WC01/02/04/08/16 is in a READ mode  
it transmits 8 bits of data, releases the SDA line, and  
monitors the line for an acknowledge. Once it receives  
this acknowledge, the CAT24WC01/02/04/08/16 will  
continue to transmit data. If no acknowledge is sent by  
theMaster, thedeviceterminatesdatatransmissionand  
waits for a STOP condition.  
Page Write  
The CAT24WC01/02/04/08/16 writes up to 16 bytes of  
data in a single write cycle, using the Page Write  
operation. The Page Write operation is initiated in the  
same manner as counter will ‘wrap around’ to address  
Doc. No. 25051-00 3/98 S-1  
6
CAT24WC01/02/04/08/16  
theByteWriteoperation,howeverinsteadofterminating  
after the initial word is transmitted, the Master is allowed  
to send up to P (P=7 for 24WC01 and P=15 for  
CAT24WC02/04/08/16)additionalbytes.Aftereachbyte  
has been transmitted the CAT24WC01/02/04/08/16 will  
respond with an acknowledge, and internally increment  
the low order address bits by one. The high order bits  
remain unchanged.  
WRITE PROTECTION  
The Write Protection feature allows the user to protect  
against inadvertent programming of the memory array.  
If the WP pin is tied to VCC, the entire memory array is  
protected and becomes read only. The CAT24WC01/  
02/04/08/16 will accept both slave and byte addresses,  
but the memory location accessed is protected from  
programmingbythedevice’sfailuretosendanacknowl-  
edge after the first byte of data is received.  
If the Master transmits more than P+1 bytes prior to  
sendingtheSTOPcondition,theaddresscounterwraps  
around’,andpreviouslytransmitteddatawillbeoverwrit-  
ten.  
READ OPERATIONS  
OnceallP+1bytesarereceivedandtheSTOPcondition  
has been sent by the Master, the internal programming  
cycle begins. At this point all received data is written to  
the CAT24WC01/02/04/08/16 in a single write cycle.  
The READ operation for the CAT24WC01/02/04/08/16  
is initiated in the same manner as the write operation  
with the one exception that the R/W bit is set to a one.  
Three different READ operations are possible: Immedi-  
ate Address READ, Selective READ and Sequential  
READ.  
Acknowledge Polling  
The disabling of the inputs can be used to take advan-  
tage of the typical write cycle time. Once the stop  
condition is issued to indicate the end of the host’s write  
operation, the CAT24WC01/02/04/08/16 initiates the  
internal write cycle. ACK polling can be initiated imme-  
diately. Thisinvolvesissuingthestartconditionfollowed  
by the slave address for a write operation. If the  
CAT24WC01/02/04/08/16 is still busy with the write  
operation, no ACK will be returned. If the CAT24WC01/  
02/04/08/16 has completed the write operation, an ACK  
will be returned and the host can then proceed with  
Immediate Address Read  
The CAT24WC01/02/04/08/16’s address counter con-  
tainstheaddressofthelastbyteaccessed, incremented  
by one. In other words, if the last READ or WRITE  
accesswas toaddressN, the READ immediatelyfollow-  
ing would access data from address N+1. If N=E (where  
E = 127 for 24WC01, 255 for 24WC02, 511 for 24WC04,  
1023 for 24WC08, and 2047 for 24WC16), then the  
counter will 'wrap around' to address 0 and continue to  
thenext read or write operation.  
Figure 6. Byte Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS  
DATA  
*
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
5020 FHD F08  
Figure 7. Page Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
DATA n  
DATA n+1  
DATA n+P  
SDA LINE  
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0  
P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16  
* = Don't care for CAT24WC01  
24WCXX F09  
Doc. No. 25051-00 3/98 S-1  
7
CAT24WC01/02/04/08/16  
clock out data. After the CAT24WC01/02/04/08/16 re-  
ceives itsslave address information (withthe R/W bit set  
to one), it issues an acknowledge, then transmits the 8-  
bit byte requested. The master device does not send an  
acknowledge but will generate a STOP condition.  
Sequential Read  
The Sequential READ operation can be initiated by  
either the immediate Address READ or Selective READ  
operations. After the 24WC01/02/04/08/16 sends initial  
8-bit byte requested, the Master will respond with an  
acknowledge which tells the device it requires more  
data. The CAT24WC01/02/04/08/16 will continue to  
output an 8-bit byte for each acknowledge sent by the  
Master. The operation is terminated when the Master  
fails to respond with an acknowledge, thus sending the  
STOP condition.  
Selective Read  
Selective READ operations allow the Master device to  
select at random any memory location for a READ  
operation. The Master device first performs a ‘dummy’  
write operation by sending the START condition, slave  
address and byte address of the location it wishes to  
read. After the CAT24WC01/02/04/08/16 acknowledge  
thewordaddress,theMasterdeviceresendstheSTART  
condition and the slave address, this time with the R/W  
bit set to one. The CAT24WC01/02/04/08/16 then re-  
sponds with its acknowledge and sends the 8-bit byte  
requested. The master device does not send an ac-  
knowledge but will generate a STOP condition.  
The data being transmitted from the CAT24WC01/02/  
04/08/16 is outputted sequentially with data from ad-  
dress N followed by data from address N+1. The READ  
operation address counter increments all of the  
CAT24WC01/02/04/08/16 address bits so that the en-  
tire memory array can be read during one operation. If  
more than the E (where E = 127 for 24WC01, 255 for  
24WC02, 511 for 24WC04, 1023 for 24WC08, and 2047  
for 24WC16) bytes are read out, the counter will “wrap  
around” and continue to clock out data bytes.  
Figure 8. Immediate Address Read Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
SDA LINE  
S
P
A
C
K
N
O
DATA  
A
C
K
SCL  
SDA  
8
9
8TH BIT  
DATA OUT  
NO ACK  
STOP  
5020 FHD F10  
Doc. No. 25051-00 3/98 S-1  
8
CAT24WC01/02/04/08/16  
Figure 9. Selective Read Timing  
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
SLAVE  
ADDRESS  
SDA LINE  
S
S
P
*
A
C
K
A
C
K
A
C
K
N
DATA n  
O
A
C
K
* = Don't Care for 24WC01  
24WCXX F11  
Figure 10. Sequential Read Timing  
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
SDA LINE  
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
5020 FHD F12  
ORDERING INFORMATION  
Prefix  
Device #  
24WC02  
Suffix  
CAT  
J
I
-1.8  
TE13  
Temperature Range  
Product Number  
24WC01: 1K  
24WC02: 2K  
24WC04: 4K  
24WC08: 8K  
24WC16: 16K  
Tape & Reel  
TE13: 2000/Reel  
Optional  
Company ID  
Blank = Commercial (0˚ - 70˚C)  
I = Industrial (-40˚ - 85˚C)  
A = Automotive (-40˚ - 105˚C)*  
Operating Voltage  
Blank: 2.5V - 6.0V  
1.8: 1.8V - 6.0V  
Package  
P: PDIP  
J: SOIC (JEDEC)  
U: TSSOP**  
24WCXX F14  
* -40˚ to +125˚C is available upon request  
** Available for 24WC01 and 24WC02  
Notes:  
(1) The device used in the above example is a 24WC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating  
Voltage, Tape & Reel)  
Doc. No. 25051-00 3/98 S-1  
9

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