CAT24WC33K-REVB [CATALYST]
EEPROM, 4KX8, Serial, CMOS, PDSO8, EIAJ, SOIC-8;型号: | CAT24WC33K-REVB |
厂家: | CATALYST SEMICONDUCTOR |
描述: | EEPROM, 4KX8, Serial, CMOS, PDSO8, EIAJ, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
文件: | 总10页 (文件大小:398K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
E
CAT24WC33/65
32K/64K-Bit I2C Serial CMOS EEPROM
TM
FEATURES
I 400 KHz I2C Bus Compatible*
I Zero Standby Current
I 1.8 to 6 Volt Read and Write Operation
I Cascadable for up to Eight Devices
I 32-Byte Page Write Buffer
I Commercial, Industrial and Automotive Tem-
perature Ranges
I Write Protection
–Bottom 1/4 Array Protected When WP at VIH
I Self-Timed Write Cycle with Auto-Clear
I 8-Pin DIP or 8-Pin SOIC
I 1,000,000 Program/Erase Cycles
I 100 Year Data Retention
I Schmitt Trigger Inputs for Noise Protection
DESCRIPTION
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
BLOCK DIAGRAM
EXTERNAL LOAD
DIP Package (P, L)
SENSE AMPS
SHIFT REGISTERS
D
OUT
1
2
3
4
8
7
6
5
A
V
CC
WP
0
ACK
A
1
V
A
SCL
SDA
CC
2
V
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SS
V
SS
256
START/STOP
SOIC Package (J, W, K, X)
SDA
LOGIC
1
2
3
4
8
7
6
5
A
A
A
V
CC
WP
0
1
2
E2PROM
128/256 X 256
XDEC 128/256
SCL
SDA
CONTROL
LOGIC
V
SS
WP
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
A0, A1, A2
SDA
Device Address Inputs
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
SCL
WP
Write Protect
SCL
STATE COUNTERS
VCC
+1.8V to +6V Power Supply
Ground
SLAVE
ADDRESS
COMPARATORS
A
A1
A2
0
VSS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Doc. No. 1049, Rev. B
Characteristics subject to change without notice
1
CAT24WC33/65
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
3
Units
mA
µA
µA
µA
V
Test Conditions
I
I
I
I
Power Supply Current
f
= 100 KHz
= GND or V
= GND to V
CC
SCL
(5)
Standby Current (V
= 5V)
0
V
V
V
SB
LI
CC
IN
CC
CC
Input Leakage Current
10
10
IN
Output Leakage Current
Input Low Voltage
= GND to V
CC
LO
OUT
V
V
V
V
–1
x 0.7
V
x 0.3
IL
CC
Input High Voltage
V
V
+ 0.5
V
IH
CC
CC
Output Low Voltage (V
Output Low Voltage (V
= +3.0V)
= +1.8V)
0.4
0.5
V
I
I
= 3.0 mA
OL1
OL2
CC
OL
V
= 1.5 mA
CC
OL
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
Units
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
8
6
pF
pF
(3)
CIN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby current (I ) = 0 µA (<900 nA).
SB
Doc. No. 1049, Rev. B
2
CAT24WC33/65
A.C. CHARACTERISTICS
= +1.8V to +6V, unless otherwise specified
V
CC
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
Min. Max.
4.5V-5.5V
Min.
Max.
Units
kHz
ns
FSCL
TI(1)
Clock Frequency
100
200
400
200
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
0.6
1.2
0.6
0.6
µs
µs
µs
µs
4.7
4
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
Parameter
Max.
Units
ms
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
tWR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Doc. No. 1049, Rev. B
3
CAT24WC33/65
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
FUNCTIONAL DESCRIPTION
The CAT24WC33/65 supports the I2C Bus data trans-
missionprotocol.ThisInter-IntegratedCircuitBusproto-
col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC33/65
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left unconnected (for hard-
warecompatibilitywithCAT24WC16). Whenhardwired,
up to eight CAT24WC33/65s may be addressed on a
single bus system (refer to Device Addressing ). When
the pins are left unconnected, the default values are
zeros.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC33/65 when this pin
is tied to Vcc, the bottom 1/4 array of memory (locations
000H to 7FFH for the 24WC65 and locations 000H to
3FFHfor24WC33)iswriteprotected. Whenleftfloating,
memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
t
t
t
F
HIGH
R
Figure 1. Bus Timing
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
AA
DH
SDA OUT
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
STOP BIT
Doc. No. 1049, Rev. B
4
CAT24WC33/65
I2C BUS PROTOCOL
comparetothehardwiredinputpins, A2, A1andA0. The
last bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
addressbyte, theCAT24WC33/65monitorsthebusand
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC33/65 then performs a Read or Write opera-
tion depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC33/65 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC33/65 responds with an acknowledge
afterreceivingaSTARTconditionanditsslaveaddress.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiv-
ing each 8-bit byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
When the CAT24WC33/65 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC33/65 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT24WC33/65 to the standby
power mode and place the device in a known state.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three bits (A2, A1, A0) are the
device address bits; up to eight 32K/64K devices may
to be connected to the same bus. These bits must
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0 R/W
5027 FHD F07
Doc. No. 1049, Rev. B
5
CAT24WC33/65
IftheMastertransmitsmorethan32bytesbeforesending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
addresspointersoftheCAT24WC33/65. Afterreceiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC33/65 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC33/65 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC33/65 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC33/65 is still busy with the
write operation, no ACK will be returned. If
CAT24WC33/65 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
The CAT24WC33/65 writes up to 32 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has
been transmitted, CAT24WC33/65 will respond with an
acknowledge,andinternallyincrementthefiveloworder
address bits by one. The high order bits remain un-
changed.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the bottom 1/4 of the memory
array (locations 000H to 7FFH for the 24WC65 and
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
A
–A
A –A
0
DATA
15
*
8
7
SDA LINE
S
P
X X X
A
C
K
A
C
K
A
C
K
A
C
K
24WC33/65 F08
Figure 7. Page Write Timing
S
T
A
R
T
S
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
O
P
A
DATA
DATA n
DATA n+31
15
*
8
7
SDA LINE
S
P
X X X
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
24WC33/65 F09
* = Don't care bit for 24WC33
X= Don't care bit
Doc. No. 1049, Rev. B
6
CAT24WC33/65
locations 000H to 3FFH for 24WC33) is protected and
becomes read only. The CAT24WC33/65 will accept
both slave and byte addresses, but the memory location
accessedisprotectedfromprogrammingbythedevice’s
failuretosendanacknowledgeafterthefirstbyteofdata
is received.
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC33/65 acknowledges,
the Master device sends the START condition and the
slaveaddressagain,thistimewiththeR/Wbitsettoone.
The CAT24WC33/65 then responds with its acknowl-
edge and sends the 8-bit byte requested. The master
device does not send an acknowledge but will generate
a STOP condition.
READ OPERATIONS
The READ operation for the CAT24WC33/65 is initiated
in the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current Ad-
dress READ, Selective/Random READ and Sequential
READ.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations.AftertheCAT24WC33/65sendstheinitial8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC33/65 will continue to output an 8-
bit byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
Immediate/Current Address Read
The CAT24WC33/65’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=4095
for 24WC33 and E=8191 for 24WC65), then the counter
will ‘wrap around’ to address 0 and continue to clock out
data. After the CAT24WC33/65 receives its slave ad-
dress information (with the R/W bit set to one), it issues
anacknowledge,thentransmitsthe8bitbyterequested.
The master device does not send an acknowledge, but
will generate a STOP condition.
The data being transmitted from CAT24WC33/65 is
outputted sequentially with data from address N fol-
lowed by data from address N+1. The READ operation
address counter increments all of the CAT24WC33/65
addressbitssothattheentirememoryarraycanberead
during one operation. If more than E (where E=4095 for
24WC33 and E=8191 for 24WC65) bytes are read out,
the counter will ‘wrap around’ and continue to clock out
data bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
24WC33/65 F10
Doc. No. 1049, Rev. B
7
CAT24WC33/65
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
SLAVE
ADDRESS
A
–A
A –A
DATA
15
8
7
0
SDA LINE
S
S
P
X X X *
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
24WC33/65 F11
* = Don't care for 24WC33
X= Don't care bit
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
5020 FHD F12
Doc. No. 1049, Rev. B
8
CAT24WC33/65
ORDERING INFORMATION
Prefix
Device #
24WC33
Suffix
(2)
-1.8
TE13
CAT
Rev B
K
I
Temperature Range
Product
Tape & Reel
TE13: 2000/Reel
Optional
Company ID
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Number
24WC33: 32K
24WC65: 64K
Die Revision
24WC33: B
24WC65: B
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
Package
P: PDIP
K: SOIC (EIAJ)
J: SOIC (JEDEC)
L: PDIP (Lead free, Halogen free)
W: SOIC (EIAJ, Lead free, Halogen free)
X: SOIC (JEDEC, Lead free, Halogen free)
* -40˚ to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 24WC33KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWB). For additional
information, please contact your Catalyst sales office.
Doc. No. 1049, Rev. B
9
REVISION HISTORY
Date
Rev.
Reason
7/8/2004
B
Added die revision to Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION and SPECIFICALLY DISCLAIMS ANY and ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1049
Fax: 408.542.1200
Revison:
B
www.catalyst-semiconductor.com
Issue date:
7/8/04
相关型号:
©2020 ICPDF网 联系我们和版权申明