CAT25020PI [CATALYST]
1K/2K/4K SPI Serial CMOS EEPROM; 1K / 2K / 4K SPI串行EEPROM CMOS
| 型号： | CAT25020PI |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 1K/2K/4K SPI Serial CMOS EEPROM |
| 文件： | 总11页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT25010/20/40
1K/2K/4K SPI Serial CMOS EEPROM
TM
FEATURES
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Self-timed write cycle
■ 10 MHz SPI compatible
■ 1.8 to 6.0 volt operation
■ Hardware and software protection
■ Low power CMOS technology
■ SPI modes (0,0 & 1,1)*
■ 8-Pin DIP/SOIC, 8-Pin TSSOP and 8-Pin MSOP
■ 16-byte page write buffer
■ Block write protection
■ Commercial, industrial, automotive and extended
– Protect 1/4, 1/2 or all of EEPROM array
temperature ranges
DESCRIPTION
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25010/
20/40 is designed with software and hardware write
protectionfeaturesincludingBlockWriteprotection.The
deviceisavailablein8-pinDIP, 8-pinSOIC, 8-pinMSOP
and 8-pin TSSOP packages.
The CAT25010/20/40 is a 1K/2K/4K Bit SPI Serial
CMOS EEPROM internally organized as 128x8/256x8/
512x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25010/20/40 features a 16-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (S, V)
MSOP Package (R, Z)*
1
2
3
4
8
7
6
5
CS
SO
WP
V
CC
SENSE AMPS
SHIFT REGISTERS
1
2
3
4
8
7
6
5
V
CS
SO
WP
CC
HOLD
SCK
HOLD
SCK
SI
V
SI
SS
V
SS
COLUMN
DECODERS
*CAT 25010/20 only
WORD ADDRESS
BUFFERS
DIP Package (P, L)
TSSOP Package (U, Y)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
V
V
CS
SO
CC
CC
SO
SI
I/O
CONTROL
SO
HOLD
SCK
SI
HOLD
SCK
SI
WP
WP
E2PROM
ARRAY
CS
V
SS
V
SPI
CONTROL
LOGIC
XDEC
SS
WP
HOLD
SCK
PIN FUNCTIONS
Pin Name
SO
Function
BLOCK
PROTECT
LOGIC
Serial Data Output
Serial Clock
DATA IN
STORAGE
SCK
WP
Write Protect
HIGH VOLTAGE/
TIMING CONTROL
VCC
+1.8V to +6.0V Power Supply
Ground
STATUS
REGISTER
VSS
CS
Chip Select
SI
Serial Data Input
Suspends Serial Input
No Connect
HOLD
NC
* Other SPI modes available on request.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1006, Rev. L
1
CAT25010/20/40
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
3
1
mA
VCC = 5.5V
FCLK = 5MHz
(6)
ISB
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
VIN = VSS or VCC
ILO
VOUT = 0V to VCC
CS = 0V
,
(5)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(5)
VIH
VCC x 0.7
2.7V≤V <5.5V
VOL1
VOH1
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) V min and V max are reference values only and are not tested.
IL
IH
(6) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
Doc. No. 1006, Rev. L
2
CAT25010/20/40
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V.
Symbol
COUT
CIN
Test Conditions
Max.
Units
pF
Conditions
Output Capacitance (SO)
8
6
VOUT=0V
VIN=0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Limits
1.8V-6.0V
Min.
2.5V-6.0V
4.5V-5.5V
Test
UNITS Conditions
Max. Min.
Max. Min. Max.
tSU
tH
Data Setup Time
Data Hold Time
50
50
20
20
75
75
DC
20
20
40
40
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
5
50
2
DC
10
50
2
(1)
tRI
(1)
tFI
Input Fall Time
2
2
2
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
40
40
CL = 50pF
(3)
tWC
tV
5
5
5
(note 2)
250
75
40
tHO
0
0
0
tDIS
tHZ
250
150
75
50
75
50
tCS
500
500
500
150
150
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tWPH
NOTE:
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
50
50
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C =50pF
L
(3)
t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Doc. No. 1006, Rev. L
3
CAT25010/20/40
the operation to be performed.
FUNCTIONAL DESCRIPTION
The CAT25010/20/40 supports the SPI bus data
transmissionprotocol.ThesynchronousSerialPeripheral
Interface (SPI) helps the CAT25010/20/40 to interface
directly with many of today’s popular microcontrollers.
The CAT25010/20/40 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25010/20/40. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25010/20/40. During a read
cycle, data is shifted out on the falling edge of the serial
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
(1)
(1)
WRITE
(2)(3)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Note:
(1) X=0 for 25010, 25020. X=A8 for 25040
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1006, Rev. L
4
CAT25010/20/40
clock for SPI modes (0,0 & 1,1).
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low all write operations are inhibited.
WP held low while CS is low will interrupt a write to the
CAT25010/20/40. If the internal write cycle has already
been initiated, WP going low will have no effect on any
write operation. Figure 10 illustrates the WP timing
sequence during a write operation.
SCK: Serial Clock
SCKistheserialclockpin.Thispinisusedtosynchronize
the communication between the microcontroller and the
CAT25010/20/40. Opcodes, byte addresses, or data
presentontheSIpinarelatchedontherisingedgeofthe
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS: Chip Select
HOLD: Hold
CSistheChipselectpin.CSlowenablestheCAT25010/
20/40 and CS high disables the CAT25010/20/40. CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25010/
20/40 draws ZERO current in the Standby mode. A high
to low transition on CS is required prior to any sequence
beinginitiated. AlowtohightransitiononCSafteravalid
write sequence is what initiates an internal write cycle.
The HOLD pin is used to pause transmission to the
CAT25010/20/40whileinthemiddleofaserialsequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
is low. The SO pin is in a high impedance state during
thetimethepartispaused, andtransitionsontheSIpins
will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held
highanytimethisfunctionisnotbeingused.) HOLDmay
be tied high directly to VCC or tied to VCC through a
resistor. Figure 9 illustrates hold timing sequence.
STATUS REGISTER
7
1
6
1
5
1
4
1
3
2
1
0
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
None
Protection
BP1
0
BP0
0
No Protection
0
1
25010: 60-7F
25020: C0-FF
25040: 180-1FF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
25010: 40-7F
25020: 80-FF
25040: 100-1FF
25010: 00-7F
25020: 00-FF
25040: 000-1FF
Doc. No. 1006, Rev. L
5
CAT25010/20/40
DEVICE OPERATION
STATUS REGISTER
Write Enable and Disable
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25010/
20/40 is busy with a write operation. When set to 1 a
write cycle is in progress and when set to 0 the device
indicatesitisready. Thisbitisreadonly. TheWEL(Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WELbitcanonlybesetbytheWRENinstructionandcan
be reset by the WRDI instruction.
TheCAT25010/20/40containsawriteenablelatch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. If WP pin is held low, the write enable latch is
reset to the write disabe state, regardless of the WREN
Instruction. WRDI instruction will disable writes (reset
the latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected,
the user may only read from the protected portion of the
array. These bits are non-volatile.
The part is selected by pulling CS low. The 8-bit read
instructionistransmittedtotheCAT25010/20/40,followed
by the 8-bit address for CAT25010/20/40 (for the 25040,
bit 3 of the read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
atthenextaddresscanbereadsequentiallybycontinuing
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 3. WRDI Instruction Timing
CS
SK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1006, Rev. L
6
CAT25010/20/40
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000hallowingthereadcycletobecontinuedindefinitely.
The read operation is terminated by pulling the CS high.
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out
on the SO line. The status register may be read at any
time even during a write cycle. Read sequece is
illustratedinFigure4. Readingstatusregisterisillustrated
in Figure 5.
WRITE Sequence
The CAT25010/20/40 powers up in a Write Disable
state.Priortoanywriteinstructions,theWRENinstruction
must be sent to CAT25010/20/40. The device goes into
Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25010/20/40.
TheCSmustbebroughthighaftertheWRENinstruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the instruction set table for address
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
1
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1006, Rev. L
7
CAT25010/20/40
device is ready for the next instruction
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Page Write
The CAT25010/20/40 features page write capability.
After the initial byte, the host may continue to write up to
16 bytes of data to the CAT25010/20/40. After each
byte of data received, lower order address bits are
internally incremented by one; the high order bits of
address will remain constant. The only restriction is that
the X (X=16 for CAT25010/20/40) bytes must reside on
the same page. If the address counter reaches the end
of the page and clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written. The CAT25010/20/40
is automatically returned to the write disable state at the
completion of the write cycle. Figure 8 illustrates the
page write sequence.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
8-bit address for 25010/20/40 (for the 25040, bit 3 of the
readdatainstructioncontainsaddressA8). Programming
will start after the CS is brought high. Figure 6 illustrates
byte write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2 and Bit 3 of the status register
can be written using the WRSR instruction. Figure 7
illustrates the sequence of writing to status register.
TheStatusRegistercanbereadtodetermineifthewrite
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
*X=0 for 25010, 25020 ; X=A8 for 25040
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1006, Rev. L
8
CAT25010/20/40
DESIGN CONSIDERATIONS
The CAT250140/20/40 powers up in a write disable
state and in a low power standby mode. A WREN
instruction must be issued to perform any writes to the
device after power up. Also,on power up CS should be
brought low to enter a ready state and receive an
instruction. After a successful byte/page write or status
register write, the CAT250140/20/40 goes into a write
disable mode. CS must be set high after the proper
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and programming is continued. On power up,
SO is in a high impedance. If an invalid op code is
received, no data will be shifted into the CAT250140/
20/40, and the serial output pin (SO) will remain in a
high impedance state until the falling edge of CS is
detected again.
Whenpoweringdown,thesupplyshouldbetakendown
to 0V, so that the CAT250140/20/40 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT250140/20/40
can be reset by refreshing the contents of the Status
Register (See Application Note AN10).
Figure 8. Page Write Instruction Timing
CS
16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
0
1
2
3
4
5
6
7
8
13 14 15
24-31
16-23
SK
SI
DATA IN
Data Data
Byte 2 Byte 3
BYTE ADDRESS
A7 A0
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
X*
0
1
0
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – – *X=0 for 25010, 25020 ; X=A8 for 25040
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1006, Rev. L
9
CAT25010/20/40
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
ORDERING INFORMATION
Prefix
Device #
Suffix
-1.8
25040
CAT
TE13
I
S
Optional
Company ID
Temperature Range
Tape & Reel
TE13: 2000/Reel
Product
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Number
25040: 4K
25020: 2K
25010: 1K
Package
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
P = 8-pin PDIP
R = 8-pin MSOP2
S = 8-pin SOIC
U = 8-pin TSSOP
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)
Z = MSOP2 (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 25040SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) CAT25010, CAT25020 only
Doc. No. 1006, Rev. L
10
REVISION HISTORY
Date
Rev.
Reason
8/3/2004
L
Updated Features
Updated DC Operating Characteristics table & notes
Copyrights, Trademarks and Patents
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2
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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typical semiconductor applications and may not be complete.
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Publication #: 1006
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Revison:
L
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Issue date:
8/3/04
www.catalyst-semiconductor.com
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