CAT25C05S16I-1.8TE13 [CATALYST]
EEPROM, 512X8, Serial, CMOS, PDSO16, SOIC-16;
| 型号： | CAT25C05S16I-1.8TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 512X8, Serial, CMOS, PDSO16, SOIC-16 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advanced
CAT25C03/05/09/17/33
2K/4K/8K/16K/32K SPI Serial CMOS E2PROM
FEATURES
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ 10 MHz SPI Compatible
■ 1.8 to 6.0 Volt Operation
■ Hardware and Software Protection
■ Zero Standby Current
■ Self-Timed Write Cycle
■ 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP
■ Page Write Buffer
■ Low Power CMOS Technology
■ SPI Modes (0,0 &1,1)
■ Write Protection
– Protect First Page, Last Page, Any 1/4 Array
or Lower 1/2 Array
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C03/05/09/17/33 is de-
signed with software and hardware write protection
features. The device is available in 8-pin DIP, 8-pin
SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP
packages.
TheCAT25C03/05/09/17/33isa2K/4K/8K/16K/32K-Bit
SPI Serial CMOS E2PROM internally organized as
256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst’s
advanced CMOS Technology substantially reduces de-
vice power requirements. The CAT25C03/05 features a
16-byte page write buffer. The 25C09/17/33 features a
32-byte page write buffer.The device operates via the
SPI bus serial interface and is enabled though a Chip
Select (CS). In addition to the Chip Select, the clock
PIN CONFIGURATION
SOIC Package (S)
SOIC Package (S16)
DIP Package (P)
TSSOP Package (U)
TSSOP Package (U14)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
16
CS
SO
WP
1
2
3
4
5
6
7
8
VCC
HOLD
NC
CC CS
CC
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
HOLD
NC
NC
NC
CS
SO
CS
SO
NC
NC
NC
WP
1
2
3
4
8
7
6
5
CS
SO
V
CC
HOLD
SCK
SI
SO
HOLD
15
14
13
12
11
10
9
HOLD
SCL
SI
WP
NC
NC
NC
NC
WP
VSS
SCK
WP
V
SS
V
V
NC
SI
SS
SS
NC
SCK
SI
V
SS
NC
BLOCK DIAGRAM
SCK
SI
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
PIN FUNCTIONS
Pin Name
SO
Function
SO
SI
Serial Data Output
Serial Clock
I/O
CONTROL
SCK
WP
E2PROM
ARRAY
CS
SPI
CONTROL
LOGIC
XDEC
Write Protect
WP
HOLD
SCK
VCC
+1.8V to +6.0V Power Supply
Ground
VSS
BLOCK
PROTECT
LOGIC
CS
Chip Select
DATA IN
STORAGE
SI
Serial Data Input
Suspends Serial Input
No Connect
HOLD
NC
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
25C128 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25068-00 2/98
1
CAT25C03/05/09/17/33
Advanced
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
ISB
Power Supply Current
(Operating Read)
0.4
0
mA
VCC = 5.5V
FCLK = 5MHz
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(3)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(3)
VIH
VCC x 0.7
4.5V≤V <5.5V
VOL1
VOH1
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25068-00 2/98
2
Advanced
CAT25C03/05/09/17/33
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
A.C. CHARACTERISTICS
Limits
1.8, 2.5
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
50
Max.
Min.
Max.
UNITS Conditions
tSU
tH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
10
20
40
40
DC
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
50
tWH
tWL
fSCK
tLZ
200
200
DC
2
50
2
10
50
2
HOLD to Output Low Z
Input Rise Time
(1)
tRI
CL = 50pF
(1)
tFI
Input Fall Time
2
2
tHD
HOLD Setup Time
HOLD HOLD Time
Write Cycle Time
Output Valid from Clock Low
Output HOLD Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
tCD
tWC
tV
10
5
200
80
tHO
tDIS
tHZ
0
0
250
100
75
50
tCS
250
250
250
100
100
100
tCSS
tCSH
NOTE:
CS Setup Time
CS HOLD Time
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25068-00 2/98
3
CAT25C03/05/09/17/33
Advanced
and the 25C03/05/09/17/33. Opcodes, byte addresses,
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK.
FUNCTIONAL DESCRIPTION
The CAT25C03/05/09/17/33 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C03/05/09/17/33 to
interface directly with many of today’s popular
microcontrollers. The CAT25C03/05/09/17/33 contains
an8-bitinstructionregister. (Theinstructionset andthe
operation codes are detailed in the instruction set table)
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25C03/
05/09/17/33 and CS high disables the CAT25C03/05/
09/17/33. CS high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway) The
CAT25C03/05/09/17/33 draws ZERO current in the
Standbymode. Ahightolow transitiononCSisrequired
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what
initiates an internal write cycle.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
PIN DESCRIPTION
WP: Write Protect
SI: Serial Input
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low, all write operations to the device
are inhibited. WP going low while CS is still low will
interruptawritetothestatusregister. Iftheinternalwrite
cycle has already been initiated, WP going low will have
no effect on any write operation to the status register.
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C03/05/09/17/33. Input data is latched on the rising
edge of the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C03/05/09/17/33. During a
read cycle, data is shifted out on the falling edge of the
serial clock.
HOLD: Hold
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C03/05/09/17/33 while in the
middleofaserialsequencewithouthavingtore-transmit
entiresequenceatalatertime.Topause,HOLDmustbe
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
(1)
(1)
WRITE
(2)(3)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Note:
(1) X=O for 25C03, 25C09, 25C17 and 25C33. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 25068-00 2/98
4
Advanced
CAT25C03/05/09/17/33
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,HOLDisbroughthigh,whileSCKislow.
(HOLD should be held high any time this function is not
being used.) HOLD may be tied high directly to VCC or
tied to VCC through a resistor. Figure 9 illustrates hold
timing sequence.
STATUS REGISTER
The status register defines the protection status of the
device. The register features three protection bits which
allow the user to protect the desirable part of the memory
array. Therearesevendifferentvariationsfortheprotec-
tion mechanism. The protection can vary from one page
to as much as half of the entire array. These areas and
associated address ranges are protected by configuring
the protection bits of the status register through WRSR
instruction. Once the three protection bits are set, the
associated memory can be read but not written until the
protection bits are reset.
STATUS REGISTER
7
0
6
0
5
0
4
0
3
0
2
1
0
IDL2
IDL1
IDL0
MEMORY PROTECTION
IDL2
IDL1
IDL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Non-Protection
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
25C03
25C05
25C09
25C17
25C33
Q1
Q2
Q3
Q4
H1
P0
Pn
00-3F 000-07F 000-0FF 000-1FF 000-3FF
40-7F 080-0FF 100-1FF 200-3FF 400-7FF
80-BF 100-17F 200-2FF 400-5FF 800-BFF
C0-FF 180-1FF 300-3FF 600-7FF C00-FFF
00-7F 000-0FF 000-1FF 000-3FF 000-7FF
00-0F 000-00F 000-01F 000-01F 000-01F
F0-FF 1F0-1FF 3E0-3FF 7E0-7FF FE0-FFF
Doc. No. 25068-00 2/98
5
CAT25C03/05/09/17/33
Advanced
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefi-
nitely.ThereadoperationisterminatedbypullingtheCS
high. Read sequece is illustrated in Figure 4. Reading
statusregisterisillustratedinFigure5. Toreadthestatus
register, RDSR instruction should be sent. The contents
of the status register are shifted out on the SO line. If a
non-volatile write is in progress, the RDSR instruction
returns a high on SO. When the non-volatile write cycle
is completed, the status register data is read out.
DEVICE OPERATION
Write Enable and Disable
The CAT25C03/05/09/17/33 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable writes
(reset the latch) to the device. Disabling writes will
protect the device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instructionistransmittedtotheCAT25C03/05/09/17/33,
followedbythe16-bitaddressfor25C09/17/33(only10-
bit addresses are used for 25C09, 11-bit addresses are
used for 25C17, and 12-bit addresses are used for
25C33. The rest of the bits are don't care bits) and 8-bit
address for 25C03/05 (for the 25C05, bit 3 of the read
data instruction contains address A8).
Figure 2. WREN Instruction Timing
SK
CS
1
1
0
SI
0
0
0
0
0
HIGH-Z
SO
Figure 3. WRDI Instruction Timing
SK
CS
0
SI
0
0
0
0
1
0
0
HIGH-Z
SO
25C128 F05
Doc. No. 25068-00 2/98
6
Advanced
CAT25C03/05/09/17/33
WRITE Sequence
Byte Write
The CAT25C03/05/09/17/33 powers up in a Write Dis-
able state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C03/05/09/17/33.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C03/05/09/17/33. The CS must be brought high
after the WREN instruction to enable writes to the
device.Ifthewriteoperationisinitiatedimmediatelyafter
the WREN instruction without CS being brought high,
the data will not be written to the array because the write
enable latch will not have been properly set. Also, for a
successful write operation the address of the memory
location(s) to be programmed must be outside the
protected address field.
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C09/17/33. (only 10-bit addresses
are used for 25C09, 11-bit addresses are used for
25C17, and 12-bit addresses are used for 25C33. The
rest of the bits are don't care bits) and 8-bit address for
25C03/05 (for the 25C05, bit 3 of the read data instruc-
tion contains address A8). Programming will start after
the CS is brought high. The low to high transition of the
CSpinmustoccurduringtheSCKlowtime, immediately
after clocking the least significant bit of the data. Figure
6 illustrates byte write sequence.
Figure 4. Read Instruction Timing
RESET
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
CS
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
SO
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
Figure 5. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
DATA OUT
HIGH IMPEDANCE
SO
3
7
6
4
5
2
1
0
MSB
25C03 F09
Doc. No. 25068-00 2/98
7
CAT25C03/05/09/17/33
Advanced
Page Write
reaches the end of the page and clock continues, the
counter will “rollover”tothefirstaddressofthepageand
overwrite any data that may have been written. The
CAT25C03/05/09/17/33 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
The CAT25C03/05/09/17/33 features page write capa-
bility. After the initial byte, the host may continue to write
upto16bytesof datatotheCAT25C03/05and32bytes
of data for 25C09/17/33. After each byte of data re-
ceived, lower order address bits are internally
incremented by one; the high order bits of address
willremain constant.The only restriction is that the X
(X=16 for 25C03/05 and X=32 for 25C09/17/33) bytes
must reside on the same page. If the address counter
To write to the status register, the WRSR instruction
should be sent. Figure 7 illustrates the sequence of
writing to status register.
Figure 6. Write Instruction Timing
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
CS
D7 D6 D5 D4 D3 D2 D1 D0
SI
0
0
0
0
0
0
1
0
ADDRESS
SO
Figure 7. WRSR Timing
CS
15
0
0
1
2
3
4
5
6
7
8
7
9
6
10
5
11
12
13
2
14
1
SCK
DATA IN
3
INSTRUCTION
4
SI
SO
Doc. No. 25068-00 2/98
8
Advanced
CAT25C03/05/09/17/33
DESIGN CONSIDERATIONS
is ignored and programming is continued. On power
up, SO is in a high impedance. If an invalid op code is
received, no data will be shifted into the CAT25C03/05/
09/17/33, and the serial output pin (SO) will remain in a
high impedance state until the falling edge of CS is
detected again.
The CAT25C03/05/09/17/33 powers up in a write
disable state and in a low power standby mode. A
WREN instruction must be issued to perform any writes
to the device after power up. Also,on power up CS
shouldbebroughtlowtoenterareadystateandreceive
an instruction. After a successful byte/page write or
status register write the CAT25C03/05/09/17/33 goes
into a write disable mode. CS must be set high after the
proper number of clock cycles to start an internal write
cycle. Accesstothearrayduringaninternal write cycle
Figure 8. Page Write Instruction Timing
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
CS
Data
Byte 1
Data
Byte 2 Byte 3
Data
Data
Byte N
SI
0
0
0
0
0
0
1
0
ADDRESS
SO
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
t
LZ
25C128 F10
Doc. No. 25068-00 2/98
9
CAT25C03/05/09/17/33
ORDERING INFORMATION
Advanced
Prefix
Device #
Suffix
-1.8
25C17
CAT
TE13
I
S
Optional
Company ID
Temperature Range
Tape & Reel
Product
Number
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
TE13: 2000/Reel
25C33: 32K
25C17:16K
25C09: 8K
25C05: 4K
25C03: 2K
Package
P = PDIP
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
S = 8-pin SOIC
S16 = 16-pin SOIC
U=8-pin TSSOP
U14 = 14-pin TSSOP
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 25C17SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
Doc. No. 25068-00 2/98
10
相关型号：
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