CAT25C16VE-1.8G [CATALYST]
EEPROM,;
| 型号： | CAT25C16VE-1.8G |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25C08, CAT25C16
8K/16K SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
I 10 MHz SPI compatible
The CAT25C08/16 is a 8K/16K Bit SPI Serial CMOS
EEPROM internally organized as 1024x8/2048x8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C08/
16 features a 32-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
thoughaChipSelect(CS). InadditiontotheChipSelect,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C08/16 is
designed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC and 8-pin TSSOP
packages.
I 1.8 to 5.5 volt operation
I 32-byte page write buffer
I Hardware and software protection
I Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
I Low power CMOS technology
I SPI modes (0,0 & 1,1)
I Industrial temperature range
I 1,000,000 program/erase cycles
I 100 year data retention
I Self-timed write cycle
I RoHS compliant “
” & “
”
8-pin PDIP, SOIC and TSSOP packages
available
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (P, L)
SOIC (S, V)
TSSOP (U, Y)
V
CC
CS
1
8
V
CC
SI
CS
SO
2
3
4
7
6
5
HOLD
SCK
SI
CAT25C08
CAT25C16
WP
WP
SO
V
SS
HOLD
SCK
PIN FUNCTIONS
Pin Name
SO
Function
V
SS
Serial Data Output
Serial Clock
SCK
WP
Write Protect
VCC
+1.8V to +5.5V Power Supply
Ground
VSS
CS
Chip Select
SI
Serial Data Input
Suspends Serial Input
HOLD
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
1
CAT25C08/16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Typ.
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
3
1
mA
VCC = 5.5V
FCLK = 5MHz
(6)
ISB
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(5)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(5)
VIH
VCC x 0.7
VOL1
VOH1
2.7V≤V <5.5V
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) V
and V
are reference values only and are not tested.
ILMIN
IHMAX
(6) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
2
CAT25C08/16
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max.
Units
pF
Conditions
Output Capacitance (SO)
8
6
VOUT=0V
VIN=0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS
CAT25Cxx-1.8
1.8V-5.5V
CAT25Cxx
2.5V-5.5V
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
50
Max. Min.
Max. Min. Max.
UNITS Conditions
tSU
tH
Data Setup Time
Data Hold Time
20
20
75
75
DC
20
20
40
40
ns
ns
50
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
ns
SCK Low Time
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
5
50
2
DC
10
50
2
MHz
ns
(1)
tRI
µs
(1)
tFI
Input Fall Time
2
2
2
µs
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
40
40
ns
ns
(3)
CL = 50pF
(2)
tWC
tV
10
5
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
250
75
40
tHO
0
0
0
tDIS
tHZ
250
150
75
50
75
50
tCS
500
500
500
150
150
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tWPH
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
50
50
(4)(5)
Power-Up Timing
Symbol
Parameter
Max.
Units
ms
tPUR
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C = 50pF
L
(3)
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) and t are the delays required from the time V is stable until the specified operation can be initiated.
t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
t
PUR
PUW
CC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
3
CAT25C08/16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C08/16 supports the SPI bus data transmis-
sion protocol. The synchronous Serial Peripheral Inter-
face (SPI) helps the CAT25C08/16 to interface directly
with many of today’s popular microcontrollers. The
CAT25C08/16 contains an 8-bit instruction register.
(The instruction set and the operation codes are de-
tailed in the instruction set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C08/16. Input data is latched on the rising edge of the
serial clock for SPI modes (0, 0 & 1, 1).
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C08/16. During a read cycle,
data is shifted out on the falling edge of the serial clock
for SPI modes (0,0 & 1,1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
t
CSH
CSS
VIH
t
t
WL
SCK
SI
WH
t
VIL
VIH
t
H
SU
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
0000 0110
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
RDSR
WRSR
READ
WRITE
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
4
CAT25C08/16
and the 25C08/16. Opcodes, byte addresses, or data
presentontheSIpinarelatchedontherisingedgeofthe
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway) The CAT25C08/16 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25C08/
16 and CS high disables the CAT25C08/16. CS high
BYTE ADDRESS
Device
Address Significant Bits
A9 - A0
Address Don't Care Bits
A15 - A10
# Address Clock Pulse
CAT25C08
CAT25C16
16
16
A10 - A0
A15 - A11
STATUS REGISTER
7
6
5
1
4
3
2
1
0
WPEN
0
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
None
Protection
BP1
0
BP0
0
No Protection
0
1
25C08: 0300-03FF
25C16: 0600-07FF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
25C08: 0200-03FF
25C16: 0400-07FF
25C08: 0000-03FF
25C16: 0000-07FF
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
0
1
1
X
X
X
1
0
1
0
1
Writable
Low
Low
High
High
Protected
Protected
Protected
Writable
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
5
CAT25C08/16
WP: Write Protect
STATUS REGISTER
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0. Figure 10 illustrates the WP timing
sequence during a write operation.
The Status Register indicates the status of the device.
TheRDY(Ready)bitindicateswhethertheCAT25C08/
16 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only. The WEL
(Write Enable) bit indicates the status of the write
enable latch. When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
HOLD: Hold
The BP0 and BP1 (Block Protect) bits indicate which
blocksarecurrentlyprotected. Thesebitsaresetbythe
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
theentirememorybysettingthesebits. Onceprotected
the user may only read from the protected portion of the
array. These bits are non-volatile.
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C08/16 while in the middle of
a serial sequence without having to re-transmit entire
sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,HOLDisbroughthigh,whileSCKislow.
HOLD should be held high any time this function is not
being used. HOLD may be tied high directly to VCC or
tied to VCC through a resistor. Figure 9 illustrates hold
timing sequence.
The WPEN (Write Protect Enable) is an enable bit for
the WP pin. The WP pin and WPEN bit in the status
register control the programmable hardware write pro-
tectfeature. Hardwarewriteprotectionisenabledwhen
WP is lowandWPENbitissettohigh. Theusercannot
write to the status register, (including the block protect
Figure 2. WREN Instruction Timing
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 3. WRDI Instruction Timing
CS
SCK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
6
CAT25C08/16
bits and the WPEN bit) and the block protected sections
in the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefi-
nitely.ThereadoperationisterminatedbypullingtheCS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be
read at any time even during a write cycle. Read
sequeceisillustratedinFigure4. Readingstatusregister
is illustrated in Figure 5.
DEVICE OPERATION
Write Enable and Disable
The CAT25C08/16 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WRENinstructionwillenable writes(setthelatch)tothe
device. WRDI instruction will disable writes(reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
WRITE Sequence
The CAT25C08/16 powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25C08/16. The device goes into
Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C08/16. The
CS must be brought high after the WREN instruction to
enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C08/16, followed
by the 16-bit address for 25C08/16. (only 10-bit ad-
dresses are used for 25C08, 11-bit addresses are used
for 25C16. The rest of the bits are don't care bits).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
Figure 4. Read Instruction Timing
CS
*
*
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
OPCODE
BYTE ADDRESS*
A
N
A
0
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the Byte Address Table.
Note: Dashed Line= mode (1, 1) – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
7
CAT25C08/16
Byte Write
bytes. After each byte of data received, lower order
address bits are internally incremented by one; the high
order bits of address will remain constant.The only
restriction is that the 32 bytes must reside on the same
page. If the address counter reaches the end of the
page and clock continues, the counter will “roll over” to
the first address of the page and overwrite any data that
may have been written. The CAT25C08/16 is automati-
cally returned to the write disable state at the completion
of the write cycle. Figure 8 illustrates the page write
sequence.
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
Therestofthebitsaredon'tcarebits). Programmingwill
start after the CS is brought high. Figure 6 illustrates
byte write sequence. During an internal write cycle, all
commands will be ignored except the RDSR (Read
Status Register) instruction.
TheStatusRegistercanbereadtodetermineifthewrite
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Page Write
The CAT25C08/16 features page write capability. After
the initial byte, the host may continue to write up to 32
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) – – – – –
Figure 6. Write Instruction Timing
CS
*
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
OPCODE
BYTE ADDRESS*
DATA IN
A
N
A
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
HIGH IMPEDANCE
SO
*Please check the Byte Address Table
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
8
CAT25C08/16
DESIGN CONSIDERATIONS
The CAT25C08/16 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
asuccessfulbyte/pagewriteorstatusregisterwrite,the
CAT25C08/16 goes into a write disable mode. CSmust
be set high after the proper number of clock cycles to
start an internal write cycle. Access to the array during
an internal write cycle is ignored and programming is
continued. On power up, SO is in a high impedance. If
an invalid op code is received, no data will be shifted
into the CAT25C08/16, and the serial output pin (SO)
will remain in a high impedance state until the falling
edge of CS is detected again.
Whenpoweringdown,thesupplyshouldbetakendown
to 0V, so that the CAT25C08/16 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C08/16 can
be reset by refreshing the contents of the Status Reg-
ister (See Application Note AN10).
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SCK
SI
DATA IN
Data Data
Byte 2 Byte 3
BYTE ADDRESS
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
0
0
1
0
A
A
0
0
N
7..1
HIGH IMPEDANCE
SO
*Please check the Byte Address Table.
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
9
CAT25C08/16
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) – – – – –
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
10
CAT25C08/16
PACKAGE INFORMATION
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
0.120
0.015
0.115
0.014
0.045
0.355
0.300
0.300
0.240
0.210
0.130
0.018
0.060
0.365
0.195
0.022
0.070
0.400
0.325
0.325
0.280
b2
D
D2
E
0.310
0.250
E1
e
0.100 BSC
eB
L
0.430
0.150
0.115
0.130
Notes:
1. Complies with JEDEC Standard MS001.
2. All dimensions are in inches.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
11
CAT25C08/16
8-LEAD 150 MIL WIDE SOIC (S, V)
E1
E
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
NOM
MAX
A1
A2
b
0.0040
0.0532
0.013
0.0098
0.0688
0.020
C
0.0075
0.1890
02284
0.149
0.0098
0.1968
0.2440
0.1574
D
E
E1
e
0.050 BSC
f
0.0099
0.0196
θ1
0°
8°
Notes:
1. Complies with JEDEC specification MS-012 dimensions.
2. All linear dimensions in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
12
CAT25C08/16
8-LEAD TSSOP (U, Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
θ1
Notes:
1. All dimensions in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
13
CAT25C08/16
TAPE AND REEL
Direction of Feed
Device Orientation
SPROKET HOLE
TOP COVER
TAPE THICKNESS (t1)
0.10mm (0.004) MAX THICK
DEVICE ORIENTATION
EMBOSSED
CARRIER
PIN 1
PIN 1
PIN 1
EMBOSSMENT
TDFN
SOIC
TSSOP
Reel Dimensions(1)
T
40mm (1.575) MIN.
ACCESS HOLE
AT SLOT LOCATION
B*
A
D*
C
N
FULL RADIUS*
TAPE SLOT IN CORE
FOR TAPE START.
2.5mm (0.098) MIN WIDTH
10mm (0.394) MIN DEPTH
* DRIVE SPOKES OPTIONAL, IF USED
ASTERISKED DIMENSIONS APPLY.
G (MEASURED AT HUB)
Embossed Carrier Dimensions
A
TAPE
SIZE
MAX
QTY/REEL
B MIN
C
D* MIN N MIN
20.2 50
G
T MAX
330
(13.00)
1.5
(0.059)
12.80 (0.504)
12.4 (0.488) _18.4_
12MM
3000
13.20 (0.5200) (0.795) (1.969) 14.4 (0.558) (0.724)
Component/Tape Size Cross-Reference
Component
Package Type
V, Y, S, U
Tape Size (W)
Part Pitch (P)
8L SOIC, TSSOP
12mm
8mm
Notes:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
14
CAT25C08/16
Embossed Carrier Dimensions (12 Pape Only)
10 PITCHES
CUMULATIVE TOLERANCE
ON TAPE 0.2mm( 0.008)
K
D
P
0
T
P
2
TOP
COVER
TAPE
E
(2)
A
0
F
W
(2)
B
B
0
K
1
0
P
CENTER LINES
OF CAVITY
D
1
FOR COMPONENTS
2.0mm X 1.2mm
AND LARGER
EMBOSSMENT
FOR MACHINE REFERENCE ONLY
INCLUDING DRAFT AND RADII
USER DIRECTION OF FEED
CONCENTRIC ABOUT B
0
Embossed Tape—Constant Dimensions(1)
Tape Sizes
D
E
P0
T Max.
D1 Min.
A0 B0 K0(2)
1.5 (0.059)
1.6 (0.063)
1.65 (0.065)
1.85 (0.073)
3.9 (0.153)
4.1 (0.161)
400
(0.016)
1.5
(0.059)
12mm
Embossed Tape—Variable Dimensions(1)
Tape Sizes
B1 Max.
F
K Max.
P2
R Min.
W
P
8.2
5.45 (0.0215)
4.5
(0.177)
1.95 (0.077)
2.05 (0.081)
30
(1.181)
11.7 (0.460) 7.9 (0.275)
12.3 (0.484) 8.1 (0.355)
12mm
(0.0323) 5.55 (0.0219)
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
(2) A B K are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to
0
0
0
0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for
24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
15
CAT25C08/16
ORDERING INFORMATION
Prefix
Device #
25C16
Suffix
-1.8
GT3
CAT
V
I
Company ID
Temperature Range
Product
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Number
25C16: 16K
25C08: 8K
Operating Voltage
Blank (VCC = 2.5V to 5.5V)
1.8 (VCC = 1.8V to 5.5V)
Package
P: PDIP
S: SOIC
U: TSSOP
L: PDIP (Lead-free, Halogen-free)
V: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
Lead Finish/Tape & Reel
G: NiPdAu Lead Plating
T: Tape & Reel
3: 3000/Reel
Notes:
(1) The device used in the above example is a 25C16VI-1.8GT3 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
16
CAT25C08/16
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
VV
25C16LI
YYWWA
VV
25C16VI
YYWWA
CSI = Catalyst Semiconductor, Inc.
25C16L = Device Code
25C08L
CSI = Catalyst Semiconductor, Inc.
25C16V = Device Code
25C08V
25C16L
25C16V
I = Temperature Range
YY = Production Year
WW = Production Week
A = Product Revision
VV = Voltage Range
1.8V - 5.5V = 18
I = Temperature Range
YY = Production Year
WW = Production Week
A = Product Revision
VV = Voltage Range
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
2.5V - 5.5V = Blank
8-Lead TSSOP
YMBV
25Y16
Y = Production Year
M = Production Month
A = Die Revision
25Y16 = Device Code
25Y08
25Y16
I = Industrial Temperature Range
V = Voltage Range
1.8V - 5.5V = 8
2.5V - 5.5V = Blank
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. A
17
REVISION HISTORY
Date
Rev.
Reason
03/21/2006
A
Initial Issue
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING
THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT
INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE
OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION,
INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst
Semiconductor product could create a situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products
with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for
sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit
diagrams illustrate typical semiconductor applications and may not be complete.
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Corporate Headquarters
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Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1016
Revison:
A
Issue date:
03/21/06
相关型号：
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