CAT28C16AKA-90T [CATALYST]
EEPROM, 2KX8, 90ns, Parallel, CMOS, PDSO24, EIAJ, SOIC-24;
| 型号： | CAT28C16AKA-90T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 2KX8, 90ns, Parallel, CMOS, PDSO24, EIAJ, SOIC-24 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT28C16A
16K-Bit CMOS PARALLEL EEPROM
TM
FEATURES
I Fast read access times: 90 ns, 120 ns, 200 ns
I End of write detection: DATA polling
I Hardware write protection
I Low power CMOS cissipation:
–Active: 25 mA Max.
–Standby: 100 µA Max.
I Simple write operation:
I CMOS and TTL compatible I/O
I 10,000 or 100,000 Program/erase cycles
I 10 or 100 year data retention
–On-chip address and data latches
–Self-timed write cycle with auto-clear
I Commercial, industrial and automotive
temperature ranges
I Fast write cycle time: 10ms max
DESCRIPTION
The CAT28C16A is a fast, low power, 5V-only CMOS
Parallel EEPROM organized as 2K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling signals the start and end of the self-timed
writecycle. Additionally, theCAT28C16Afeatureshard-
ware write protection.
The CAT28C16A is manufactured using Catalyst’s ad-
vancedCMOSfloatinggatetechnology. Itisdesignedto
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 24-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
2,048 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
& LATCHES
A –A
4
10
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1076, Rev. D
1
CAT28C16A
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, K, W, X)
PLCC Package (N, G)
A
A
1
24
23
22
21
20
19
18
17
16
15
14
13
V
A
A
A
A
V
A
A
1
24
23
22
21
20
19
18
17
16
15
14
13
7
6
5
4
3
2
1
0
0
1
2
CC
8
7
6
5
4
3
2
1
0
0
1
2
CC
8
2
2
A
3
A
3
4
3 2 1 32 31 30
9
9
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
A
A
4
A
WE
4
WE
6
5
4
3
2
1
0
8
9
A
5
OE
A
OE
5
NC
NC
OE
A
A
6
A
A
6
A
10
10
A
7
A
CE
7
CE
TOP VIEW
A
8
A
I/O
7
I/O
8
I/O
7
I/O
10
11
12
13
I/O
I/O
I/O
V
9
I/O
I/O
I/O
V
9
10
6
6
CE
10
11
12
I/O
5
I/O
10
11
12
I/O
5
I/O
NC
I/O
7
4
4
I/O
I/O
I/O
3
I/O
3
0
SS
SS
6
14 15 16 17 18 19 20
PIN FUNCTIONS
Pin Name
Function
Address Inputs
A0–A10
I/O0–I/O7
CE
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
5V Supply
OE
WE
VCC
VSS
Ground
NC
No Connect
MODE SELECTION
Mode
CE
WE
OE
L
I/O
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
L
L
H
DOUT
DIN
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Max.
10
Units
pF
Conditions
(1)
CI/O
Input/Output Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
(1)
CIN
6
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1076, Rev. D
2
CAT28C16A
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min
100,000
100
Max
Units
Cycles/Byte
Years
(1, 7)
NEND
(1, 7)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
VCC = 5V 10%, unless otherwise specified.
Limits
Typ
Symbol
Parameter
Min
Max
Units
Test Conditions
ICC
VCC Current (Operating, TTL)
35
mA
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
(5)
ICCC
VCC Current (Operating, CMOS)
25
mA
CE = OE = VILC,
f = 1/tRC min, All I/O’s Open
ISB
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
1
mA
CE = VIH, All I/O’s Open
(6)
ISBC
100
µA
CE = VIHC,
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
–10
–10
10
10
µA
µA
VIN = GND to VCC
ILO
VOUT = GND to VCC
CE = VIH
,
(6)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
VCC +0.3
0.8
V
V
V
V
V
(5)
VIL
–0.3
2.4
VOH
VOL
VWI
IOH = –400µA
0.4
IOL = 2.1mA
3.0
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
(5) V
(6) V
= –0.3V to +0.3V.
ILC
= V –0.3V to V +0.3V.
IHC
CC
CC
(7) For the CAT28C16A-20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years.
Doc. No. 1076, Rev. D
3
CAT28C16A
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V 10%, unless otherwise specified.
28C16A-9028C16A-12
28C16A-20
Min
Symbol
tRC
Parameter
Min
Max
Min
Max
Max
Units
ns
Read Cycle Time
90
120
200
tCE
CE Access Time
90
90
50
120
120
60
200
200
80
ns
tAA
Address Access Time
OE Access Time
ns
tOE
ns
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
0
0
0
0
0
0
ns
(1)
tOLZ
ns
(1)(2)
tHZ
50
50
50
50
55
55
ns
(1)(2)
tOHZ
ns
(1)
tOH
0
0
0
ns
Figure 1. A.C. Testing Input/Output Waveform(3)
2.4 V
2.0 V
INPUT PULSE LEVELS
0.45 V
REFERENCE POINTS
0.8 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
Doc. No. 1076, Rev. D
4
CAT28C16A
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V 10%, unless otherwise specified.
28C16A-9028C16A-12
28C16A-20
Max Min Max
10
Symbol
tWC
Parameter
Min
Max
Min
Units
ms
ns
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
5
5
tAS
0
100
0
0
100
0
10
100
0
tAH
ns
tCS
ns
tCH
CE Hold Time
0
0
0
ns
(2)
tCW
CE Pulse Time
110
0
110
0
150
15
15
150
50
10
50
5
ns
tOES
tOEH
OE Setup Time
ns
OE Hold Time
0
0
ns
(2)
tWP
WE Pulse Width
Data Setup Time
Data Hold Time
110
60
0
110
60
0
ns
tDS
tDH
tDL
ns
ns
Data Latch Time
Write Inhibit Period After Power-up
5
10
5
10
ns
(1)
tINIT
.05
100
.05
100
20
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
Doc. No. 1076, Rev. D
5
CAT28C16A
DEVICE OPERATION
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Read
Data stored in the CAT28C16A is transferred to the data
bus when WE is held high, and both OE and CE are held
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
OLZ
t
HZ
DATA VALID
OH
HIGH-Z
DATA OUT
DATA VALID
t
AA
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
DL
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1076, Rev. D
6
CAT28C16A
Byte Write
DATA Polling
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O7 (I/O0–I/O6 are indeter-
minate) until the programming cycle is complete. Upon
completion of the self-timed byte write cycle, all I/O’s will
output true data during a read cycle.
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
DL
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Figure 6. DATA Polling
ADDRESS
CE
WE
OE
t
OEH
t
OES
t
OE
t
WC
= X
I/O
7
D
= X
D
D
= X
OUT
IN
OUT
Doc. No. 1076, Rev. D
7
CAT28C16A
HARDWARE DATA PROTECTION
teristics), provides a 5 to 20 ms delay before a write
sequence, after VCC has reached 3.0V min.
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28C16A.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
(1) VCC sense provides for write protection when VCC
falls below 3.0V min.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
(2) A power on delay mechanism, tINIT (see AC charac-
Doc. No. 1076, Rev. D
8
CAT28C16A
ORDERING INFORMATION
Prefix
Device #
Suffix
T
CAT
28C16A
N
I
-20
Optional
Company ID
Product
Number
Temperature Range
Tape & Reel
*
Package
Speed
P: PDIP
90: 90ns
N: PLCC
J: SOIC (JEDEC)
K: SOIC (EIAJ)
12: 120ns
20: 200ns
L: PDIP (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
X: SOIC (EIAJ) (Lead free, Halogen free)
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28C16ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel).
Doc. No. 1076, Rev. D
9
REVISION HISTORY
Date
Revision Comments
3/30/2004
A
B
C
D
Added Green packages in all areas
Delete data sheet designation
Update Block Diagram
Update Ordering Information
Update Revision History
Update Rev Number
04/19/04
09/21/04
09/22/04
Update Features
Update AC Characteristics tables
Update Ordering Information
Minor changes
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Publication #: 1076
Revison:
D
Issue date:
09/22/04
相关型号：
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